# 3D NAND

> Source: https://aiwiki.ai/wiki/3d_nand
> Updated: 2026-08-01
> Categories: AI Hardware, AI Infrastructure, Computer Science
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3D NAND is the vertical architecture that [NAND flash memory](/wiki/nand_flash) adopted when shrinking cells sideways stopped working. Instead of laying memory cells out on the surface of a wafer and making them smaller each generation, a 3D NAND die is built as a stack of horizontal conducting layers (the word lines) with narrow vertical holes punched down through the whole stack. A cylindrical channel is grown inside each hole, and every place where a word line crosses a channel becomes one memory cell. Density then improves by adding layers rather than by shrinking features, which is why NAND has kept getting cheaper per bit through a decade in which [lithography](/wiki/asml) scaling became ruinously expensive for logic.

The industry has settled on layer count as the headline number for a NAND generation, and the number is genuinely meaningful: Kioxia's 332-layer generation packs 59 percent more bits into the same area than its 218-layer generation [15]. It is also, treated carelessly, one of the most misleading figures in semiconductors. Vendors count differently, several have stopped publishing the number at all, and the total layers in a stack are not the same as the layers that store data. A teardown of one Chinese fifth-generation part found 294 layers of which only 232 were active [23].

This article covers the vertical architecture itself: how the structure is built, what limits it, and where vendors genuinely differ. The cell physics of storing charge, the SLC/MLC/TLC/QLC ladder, controllers, wear management and the NAND market belong to the parent topic and are covered there.

## Why planar NAND stopped scaling

Planar NAND stored charge on a floating gate, a conductive island isolated by oxide. Two problems ended that approach at around the 20 nm node, and they compound each other.

The first is cell-to-cell interference. A floating gate is a capacitively coupled electrode, and as the spacing between neighbouring gates shrinks, the coupling between them grows. Programming one cell then shifts the apparent threshold voltage of its neighbours. A 2010 Stanford dissertation on scaled planar floating-gate NAND called this "the biggest challenge in the scaling of NAND flash memory," and noted that it gets worse with multi-level cells because the window between states is already narrow [37]. The same work identified the mechanism that makes it unfixable: satisfactory operation needs a gate coupling ratio above 0.6, which is achieved by wrapping the control gate around the floating gate, and "with decreasing spacing between adjacent cells, there is no longer any space for wrapping the control-gate in between floating-gates" [37]. Jim Handy of Objective Analysis put the consequence plainly in 2016: the floating gate was seeing "an undesirable reduction in the capacitive coupling to the control gate" [2]. Samsung, announcing its first 3D part, gave the same diagnosis: as process technology moved into the 10 nm class and beyond, "concern for a scaling limit arose, due to the cell-to-cell interference that causes a trade-off in the reliability of NAND flash products" [1]. Its own tutorial material puts the threshold at 20 nm, below which the chance of charge leaking between cells rises sharply [20].

The second is that a smaller floating gate holds fewer electrons. The stored charge is quantised, so as the count falls the loss of a handful of electrons to leakage moves the threshold voltage by a proportionally larger amount, and eventually the state of a cell becomes a statistical question rather than a deterministic one. The Stanford work named this as the end of the road: "the ultimate intrinsic limits of NAND flash memories are likely to be due to statistical fluctuations induced by too few electrons stored" [37]. Its conclusion in 2010, five years before Intel and Micron shipped their first 3D part, was that once a cell is limited by the number of electrons it holds, "instead of scaling cell-area, it is better to integrate cells in 3D to increase density," and it named Toshiba's bit cost scalable cell as the direction to pursue [37].

Both problems are geometric, and neither is fixed by a better process. The way out was to stop shrinking and start stacking, and to change the storage medium at the same time. Charge trap flash replaces the conductive floating gate with an insulating silicon nitride layer that holds charge in discrete traps. Because the layer does not conduct, charge cannot redistribute along it, so a single continuous nitride film can run the full height of a vertical string and still act as separate cells at each word line. Samsung had developed the charge trap architecture in 2006 and described it as the enabler for the vertical structure [1].

## The vertical string

A 3D NAND array starts with alternating film deposition. Pairs of layers are deposited on the wafer by chemical vapour deposition, over and over, to build what the industry calls the mould or the stack. Samsung deposits alternating silicon nitride and silicon dioxide; Toshiba's original approach used alternating conductive polysilicon and silicon dioxide [2]. In the nitride-oxide (ONON) flow, the nitride is sacrificial: after the holes are etched, it is stripped out through slits and replaced with metal, which is why this route is called replacement gate or gate-last. Metal word lines have much lower resistance than polysilicon, and the industry converged on them. Micron's 176-layer node in November 2020 was its second-generation replacement-gate design and the point at which it abandoned floating gate for charge trap [33].

With the stack built, a hard mask is patterned and the memory hole is etched from the top surface all the way down to the substrate. A dielectric liner and the charge trap layer are deposited on the hole walls, and a polysilicon channel is grown inside. The result at each word line crossing is a transistor whose gate completely surrounds a cylindrical channel, a gate-all-around device. Jan Van Houdt of imec refers to it as "the currently used gate-all-around (or cylindrical) architecture" and contrasts it with a proposed trench variant that would double density at the cost of a second high aspect ratio etch [3].

The original proposal is Toshiba's. H. Tanaka and colleagues presented "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High Density Flash Memory" at the 2007 Symposium on VLSI Technology, giving the family its name: BiCS, for bit cost scalable [3]. Kioxia, Toshiba's memory business as it exists today, dates BiCS FLASH to that 2007 work [17]. Samsung shipped first. On 6 August 2013 it announced mass production of a 128 Gb die stacking 24 cell layers, built on charge trap flash and connected by "vertical interconnect process technology" that punched holes from the top layer to the bottom [1]. Intel and Micron took a different path and extended the floating gate into three dimensions, the only vendors to do so; [TechInsights](/wiki/techinsights) measured their 32-layer die at 2.28 Gb/mm2 against 1.01 Gb/mm2 for Samsung's 32-layer V-NAND [32].

One structure that gets little attention outside the fabs is the word line contact. Every layer in the stack has to be reachable individually by the row decoder, which is done by terminating the layers in a staircase so that each layer's edge is exposed and can be contacted from above. The staircase is dead area, it grows with the stack, and it eats into the core array [36]. Vendors attack it from several directions. Kioxia's roadmap material describes moving from one word line lane per staircase level to two and four, and placing contacts across the width of the staircase rather than along its length, at the cost of a deeper etch with tighter profile and critical dimension control [36]. Samsung's ninth generation introduced what it calls Through Cell Metal Contact, a contact that pierces down through the cell gate word lines rather than stepping around them, alongside a scheme that divides the word lines and removes dummy channel holes to recover area [19]. TechInsights identified the same through-type cell metal contact as the distinguishing feature of the 286-layer V9 die [35].

The scale of the etch problem is easiest to grasp from Samsung's own productivity note. Its sixth-generation V-NAND, which Samsung's tutorial material puts at 136 layers, cut the number of channel holes needed for a 256 Gb chip from 930 million to 670 million, which it credited with roughly 20 percent better manufacturing productivity [20]. Every one of those hundreds of millions of holes has to be drilled through the full stack, land on target, and come out the same shape as its neighbours.

## High aspect ratio etch

The channel hole etch, called memory hole etch by some vendors and high aspect ratio contact (HARC) etch by others, is the step that bounds the whole technology. Aspect ratio is the depth of the hole divided by its width, and it has risen relentlessly. In 2016 Applied Materials' Er-Xuan Ping put 32- and 48-layer devices at 30:1 to 40:1, and 64-layer devices at 60:1 to 70:1, adding that at the time "the etching and hard mask technologies are not necessarily available for 60:1 or 70:1" [2]. By 2021 Kevin Heidrich of Onto Innovation was writing about a final structure with an aspect ratio over 120:1 [4]. A 2024 analysis written by Counterpoint Research in collaboration with Lam Research put the requirement above 100:1 for a 1,000-layer device built as multiple tiers, with a hole size around 100 nm [5]. Maarten Rosmeulen of imec gave concrete dimensions for a 128-layer part in 2022: a hole roughly 6 to 8 micrometres deep and about 120 nanometres across [3].

Three physical effects make this hard.

**Aspect ratio dependent etching.** As the hole gets deeper, the flux of ions and neutral reactants reaching the bottom falls, so the etch slows down as it proceeds. The Counterpoint and Lam analysis names the effect (ARDE) and treats it as the primary barrier to depth, because a slower etch means a longer, more expensive process step and eventually a hole that simply will not finish [5]. Rosmeulen made the economic version of the point: "There are advances in the etch technology to etch deeper holes in one go, but it won't go faster. You can't increase the speed of the etch. So if the process flow get dominated by the deposition and etch, and those process steps don't increase in cost efficiency, then adding more layers is not as efficient anymore to reduce the cost" [3].

**Profile distortion.** A perfectly cylindrical hole is the goal and nobody gets one. Polymer from the etch chemistry deposits on the mask and near the top of the feature, narrowing the opening and choking off ion flux, which produces bowing (a hole wider in the middle than at the top), tapering (a hole that narrows with depth), striation and twisting [5]. Because the cell is defined by the hole, any deviation in the hole's critical dimension from top to bottom becomes a difference in cell characteristics between the top and bottom word lines of the same string.

**Material stack transitions.** The etch has to cut through hundreds of alternating layers of two different materials without changing behaviour at every interface.

The main industrial answer since 2019 has been cryogenic etching, running the wafer well below zero to increase adsorption of reactive species while suppressing lateral etching. Lam Research introduced Lam Cryo 3.0 on 31 July 2024 and claims memory channels etched as deep as 10 microns with less than 0.1 percent deviation in critical dimension from top to bottom, at 2.5 times the rate of a conventional dielectric etch, using temperatures as low as minus 60 degrees Celsius [5][7]. Lam describes the features as "more than 50 times deeper than their width" and states an installed base, as of the 2024 paper, of more than 7,500 etch chambers with nearly 1,000 running cryogenic processes and over five million wafers processed [5][7]. Lam's etch general manager Harmeet Singh wrote in July 2024 that "the technologies and processes that got us from 2D to 3D, and from 64- to 232-layer 3D NAND are not capable of getting us to 1,000 layers without new breakthroughs" [6].

Etching the hole is not the end of it. Xi-Wei Lin of Synopsys pointed out that the charge trap and dielectric layers then have to be deposited uniformly down the full depth of the hole, a few nanometres thick, and that the word lines have to be backfilled with metal afterwards [3]. Dave Hemker of Lam described tungsten backfill as "a non-line-of-sight deposition" into "caves and tunnels" where a mis-tuned precursor plates out at the entrance and leaves voids behind [2].

This is why 3D NAND turned the equipment mix upside down. In planar NAND the critical, expensive step was lithography. In 3D NAND the patterning is done at relaxed 40 nm to 20 nm design rules and the money moves to deposition and etch. SEMI's Christian Dieseldorff estimated in 2016 that equipment for a 2D NAND fab cost 30 to 45 million dollars per 1,000 wafer starts per month, against 50 to 65 million dollars for 3D NAND, "because more equipment like CVD and etch tools are needed" [2].

## String stacking

There is a limit to how deep one etch can go, and it arrived well before the layer race did. SK hynix states it directly: "existing etching equipment can only etch around 100 layers at a time" [12]. Applied Materials' Ping said in 2016 that single-string 3D NAND "hits the wall at 128 layers" [2].

The workaround is string stacking, also called deck or tier stacking. The vendor builds one deck to completion, etches and fills its holes, then deposits a second stack on top and etches a second set of holes that must land precisely on the first. Two decks of 96 layers replace one impossible etch of 192. Micron demonstrated the idea early, reportedly building a 64-layer device from two 32-layer stacks [2].

Almost every high-layer-count product now shipping is multi-deck. TechInsights found two decks in Samsung's 176-layer, SK hynix's 176-layer, Micron's 176-layer and YMTC's 232-layer parts [34]. SK hynix crossed 300 layers by going to three: its 321-layer part, in mass production from 20 November 2024, uses what the company calls "3 plugs" process technology, in which the plug (hole) process is run three times and the results connected by an optimised follow-up step [11]. Kioxia's and SanDisk's 332-layer BiCS10 is reported by Blocks & Files as a triple stack of decks above 100 layers each [28]. Samsung, unusually, has stayed with two decks and competed on how many layers it can put in each: its ninth-generation V-NAND announcement credits "advanced 'channel hole etching' technology" with "simultaneous drilling of the industry's highest cell layer count in a double-stack structure" [18].

The costs of string stacking are real and fall into three buckets.

**Alignment.** The second deck's holes are patterned lithographically and can be registered accurately to the surface, but both the first deck's holes and the second's wander with depth. Heidrich put the tolerance problem starkly: the manufacturer has to land "these 80-100nm holes, drilled through microns of material, on top of another 80-100nm hole," and get it right trillions of times [4]. Some vendors etch landing zones or chamfers into the top of the first deck to widen the target [4].

**The joint.** The interface between decks is a discontinuity in an otherwise continuous channel. It has to conduct, it has to admit cleaning and deposition chemistry for the storage layers, and it introduces cell-to-cell variation that a single-etch string does not have.

**Compounding yield loss.** Ping's warning has aged well: "When you stack, the yield loss from defects continues building up. That will be the limitation. Plus, everything will be limited by stress. If you put too much film, then the stress presents a limitation" [2]. In 2016 he expected string stacking to run out at or near 300 layers. Products have passed that, but only with new stress and warpage management.

## Where the periphery goes

A NAND die is not only an array. It also carries page buffers, charge pumps, word line drivers, sense amplifiers and the input/output interface, collectively the periphery or CMOS logic. Where that logic sits is the design decision on which vendors most visibly differ, and the terminology is a minefield because four companies invented four names for overlapping ideas.

**Periphery beside the array.** The original arrangement, which Kioxia labels CNA and used up to its fifth BiCS generation [13]. It wastes die area. YMTC estimates that conventional 3D NAND spends 20 to 30 percent of the die on periphery, and that this exceeds 50 percent past 128 layers [22].

**Periphery under the array, on the same wafer.** Build the CMOS first, then grow the memory stack on top of it. This recovers most of the wasted area. The names differ by vendor and the underlying idea is the same:

- **CuA (CMOS under Array)** is Micron's term, used from its first 32-layer 3D NAND with Intel [34]. TechInsights' analysis of that die describes the CMOS decoders and sense amplifiers sitting under the array to reach 2.28 Gb/mm2, with word line drivers underneath shortening the word lines [32]. Micron carried CuA through the 176-layer and 232-layer nodes [9][33].
- **PUC (Periphery Under Cell)** is SK hynix's term, adopted from its 96-layer generation [34]. SK hynix markets the combination of charge trap flash and PUC as **4D NAND**, which is a trade name for a 3D structure rather than a different geometry; Semiconductor Engineering called it "another variation of 3D NAND, with a smaller cell area per unit" [3]. A later refinement the company calls All PUC shrinks the periphery until it is no larger than the cell array above it [12].
- **COP (Cell Over Periphery)** is Samsung's term. Samsung came to it late, at the 176-layer seventh generation, and TechInsights attributes a significant die size reduction to the change [34]. Samsung's own Tech Day 2022 material claims a 42 percent bit density improvement from entering "the cell over peripheral (COP) era" [21].

The catch with all three is thermal. The logic transistors are finished before the memory stack is built, and then they have to survive every deposition and anneal used to build hundreds of layers above them. Kioxia describes its own CUA generation as stacking the array on completed CMOS and then applying high-temperature annealing, "a process that compromised transistor performance characteristics" [14].

**Periphery on a separate wafer, bonded.** The fix is to build the two halves independently and join them. The logic wafer runs a normal logic flow at whatever node and thermal budget suits it; the array wafer runs a memory flow with an unconstrained thermal budget; the two are then flipped face to face and bonded, with electrical connections made through a dense field of metal pads.

- **Xtacking** is YMTC's implementation and the first in production. Announced at Flash Memory Summit in August 2018 after what the company describes as nine years of development and four of verification, it bonds a CMOS wafer to a memory array wafer through millions of metal vertical interconnect accesses, billions per die [22]. YMTC claims the arrangement enables "DRAM-like high I/O speed" because the periphery is fabricated on a logic node chosen for interface performance, and that the modularity cuts product development time by at least three months and manufacturing cycle time by 20 percent [22]. TechInsights records YMTC applying Xtacking from its 64-layer second generation [34].
- **CBA (CMOS directly Bonded to Array)** is Kioxia's and SanDisk's implementation, first shipped in the eighth BiCS generation. Kioxia's engineering description is precise: CMOS and array are formed on separate silicon wafers and joined by copper direct bonding, "electrically connecting CMOS and the cell array via the Cu bonding pads" [13]. The company sets out the progression as CNA up to generation 5, CUA at generation 6, and CBA from generation 8 [13]. It attributes a 35 percent improvement in cell current and an interface speed of 3.6 Gbps to the change, along with roughly 50 percent higher bit density, 20 percent better write performance and about 30 percent lower write power against the 162-layer sixth generation [13][14].

What bonding costs is precision. Kioxia states that the bonding surfaces must be planarised to nanometre-scale step heights by chemical mechanical polishing and that wafer alignment must hold to "within a few hundred nanometers or less" across a 300 mm wafer, an accuracy it compares to holding one millimetre across a one kilometre disc [13][14]. It also costs a wafer: two wafers are consumed per finished die, so the logic wafer's yield multiplies against the array wafer's, and a defective die on either side scraps a good die on the other. That is why bonding only pays once the periphery is large enough, or the thermal conflict severe enough, to be worth the loss.

As of August 2026 the remaining two large vendors are converging on the same answer. SK hynix, whose shipping parts still use monolithic PUC, is reported by the Korea Economic Daily to be targeting hybrid-bonded NAND at its V10 generation, with development completing at the end of 2026 and mass production in 2027 [29]. Samsung's tenth-generation V-NAND is reported to use a bonded structure with cells and periphery on separate wafers, an arrangement Blocks & Files calls Cell-on-Periphery [28]. Neither company had published a technical paper describing a shipping bonded product at the time of writing.

## The layer race, and what layer counts actually mean

More layers really do mean more bits, and the gains are large. Micron put the areal bit density of its 232-layer die at more than 45 percent above its 176-layer generation [8], and reached 14.6 Gb/mm2, which it claimed was 35 to 100 percent ahead of competing TLC products at the time [9]. Kioxia claims 59 percent higher bit density at 332 layers than at 218, though it credits improved lateral density as well as the extra layers [15]. For context on the trajectory, TechInsights measured the leading 128-layer TLC dies of 2021 and 2022 between 6.96 and 8.47 Gb/mm2 [34], and Electronics Weekly reported Samsung's 286-layer V9 QLC part at 28.5 Gb/mm2 [24].

That said, layer counts are marketing figures before they are engineering figures, and they should be read with four cautions.

**Total layers are not active layers.** A stack contains word lines that store data, dummy word lines that do not, and select gates at the top and bottom of each string that switch it onto the bit line. TechInsights' analysis of the Intel and Micron 32-layer part counted 32 active word lines plus 6 dummy word lines, 3 at the top and 3 at the bottom, for 40 gates in total [32]. The gap widens with height. Reporting TechInsights' analysis in February 2025, Electronics Weekly described a shipping YMTC fifth-generation TLC part with 294 layers of which only 232 were active, meaning 62 dummy layers, against 253 total and 232 active in the fourth generation [23]. The active word line count did not increase between the two generations even though the advertised number rose by 41. Bit density came in around 20 Gb/mm2, level with SK hynix and below Kioxia's 22.9 [23].

**Several vendors no longer publish the number.** Micron's July 2024 announcement of volume production of its ninth-generation NAND states a transfer speed of 3.6 GB/s, a package size and a density comparison, and no layer count at all [10]; trade press reporting puts G9 at 276 layers [28]. Samsung has not published a layer count for a V-NAND generation in years: the April 2024 ninth-generation release describes "the industry's smallest cell size and thinnest mold" and a double-stack structure without a number [18]. The public figures for those parts come from teardowns.

**Generation numbers do not track layer counts.** Kioxia sampled its 332-layer tenth-generation BiCS on 3 July 2026 and its 230-layer ninth generation on 30 July 2026, three weeks later [15][16]. The ninth generation is the cheaper, lower-capacity line aimed at AI PCs and smartphones, built on the same CBA CMOS as the tenth [16]. A higher generation number in the same family can mean a lower stack.

**A roadmap is not a shipping date.** Kioxia's own presentation at IWM 2024 in Seoul in June 2024, reported by Blocks & Files, projected BiCS 9 at 300 layers and BiCS 10 at over 400, on a path to 1,000 word line layers and 100 Gbit/mm2 by 2027 [36]. The parts that actually sampled two years later were 230 layers and 332 layers [15][16]. The direction was right and the numbers were not, which is the normal outcome for a memory roadmap slide and the reason a projected layer count should never be quoted as a product specification.

| Vendor | Generation | Layers | Whose figure | Milestone |
| --- | --- | --- | --- | --- |
| Samsung | V1 | 24 | Samsung [1] | Mass production 6 August 2013, 128 Gb, first commercial 3D NAND |
| Samsung | V6 | 136 | Samsung [20] | Described in Samsung's own tutorial material |
| Samsung | V7 | 176 | TechInsights [34] | First Samsung generation with cell over periphery; two decks |
| Samsung | V8 | 236 | Samsung [21] | Cited at Samsung Tech Day 2022 |
| Samsung | V9 | 286 | TechInsights, via Electronics Weekly [24] | Samsung began TLC mass production April 2024 [18], QLC September 2024 [24], without stating a layer count |
| Samsung | V10 | 400 | Korean press reports [30] | Reported in mass production during 2026; no Samsung figure published |
| SK hynix | 96-layer 4D | 96 | SK hynix [12] | 2018; first PUC generation |
| SK hynix | 238-high | 238 | SK hynix [11] | Claimed industry first, June 2023 |
| SK hynix | 321-high | 321 | SK hynix [11] | Mass production announced 21 November 2024; three plug processes |
| Micron (with Intel) | 1st gen 3D | 32 active, 6 dummy | TechInsights [32] | Floating gate, CMOS under array |
| Micron | 176-layer | 176 | Micron [33] | November 2020; second-generation replacement gate, charge trap |
| Micron | 232-layer | 232 | Micron [9] | 26 July 2022; six-plane TLC, 14.6 Gb/mm2 |
| Micron | G9 | not disclosed | reported as 276 [28] | Volume production announced 30 July 2024 [10] |
| Kioxia and SanDisk | BiCS 6 | 162 | Kioxia [14] | 2021; CMOS under array |
| Kioxia and SanDisk | BiCS 8 | 218 | Kioxia [14] | First CBA generation |
| Kioxia and SanDisk | BiCS 9 | 230 | Kioxia [16] | Samples 30 July 2026; cost-optimised line |
| Kioxia and SanDisk | BiCS 10 | 332 | Kioxia [15] | Samples 3 July 2026; 1 Tb TLC, 4.8 Gb/s |
| YMTC | Gen 4 (Xtacking 3.0) | 253 total, 232 active | TechInsights, via Electronics Weekly [23] | YMTC does not publish layer counts |
| YMTC | Gen 5 (Xtacking 4.0) | 294 total, 232 active | TechInsights, via Electronics Weekly [23] | 62 dummy layers; reported February 2025 |

The 232-layer priority claim is a good illustration of how carefully these announcements have to be read. Micron announced volume production of what it called the "world's first 232-layer NAND" on 26 July 2022 [9][31]. YMTC introduced its X3-9070 a week later, on 2 August 2022, and the claim it actually made was for Xtacking as an architecture; its release does not state a layer count [22][23]. The widely repeated line that YMTC shipped 232-layer NAND first does not survive checking against the two announcements.

## Where the ceiling is

Nobody in the industry claims a hard physical limit, and the ones who have named a number have generally been wrong. In 2016 the expectation was that string stacking would run out at or near 300 layers [2]. Samsung's Kinam Kim predicted 1,000-layer flash by 2030 in an IEDM keynote in 2021, a target Samsung repeated at its 2022 Tech Day [3][21] and which Lam Research has adopted as its own roadmap framing [6]. Handy's response is the industry's institutional memory talking: "There's no physical limit when people say we can't go past this number of layers. In the world of semiconductors, there are always people saying we can't do this" [3].

The binding constraints are economic and mechanical rather than fundamental.

**Etch time and capital intensity.** Every added layer lengthens the deposition and etch steps and adds tool-hours per wafer. IBM's Roman Pletka framed the trade-off in 2022: increasing layers is challenged "due to the high aspect ratio etching process, but also by CapEx because the time to manufacture a chip increases with the layer count" [3]. The Counterpoint and Lam analysis makes the same point from the supply side: "as the number of layers rise, it becomes increasingly costly to add more storage capacity," and without innovation in deposition and etch tools "this evolution will struggle to improve the cost efficiency of the NAND FLASH storage products" [5]. Rosmeulen read the vendors' own public roadmaps in 2022 as already slower than the historical trend, and attributed the slowdown to the investment required [3].

**Stress and wafer bow.** A tall stack of dissimilar films is a stressed structure. Lin described both failure modes: locally, deep slits cut through the stack leave high aspect ratio walls that can deflect and touch, destroying yield; globally, "by putting so many materials on top of each other, and cutting different patterns, this can create global stress and can cause a wafer to warp, which will make it impossible to handle in the fab because a wafer has to be flat" [3]. Wafer stress management, to control bow and enable taller devices, is listed alongside word line pitch scaling and metallisation as an explicit development track [5]. SK hynix credited low-stress materials, plus technology that automatically corrects alignment between plugs, for making its three-plug 321-layer stack manufacturable [11].

**Channel resistance.** The string is a single polysilicon channel running the full height of the stack, and polysilicon is a poor conductor with grain boundaries that scatter carriers. Make the string taller and the current available to read a cell falls, which slows sensing and narrows the margin between programmed states. Kioxia's roadmap material treats this as a first-order problem and proposes converting the channel from polysilicon to single-crystalline silicon by metal-induced lateral crystallisation [36]. Bonding helps here too: Kioxia attributes a 35 percent improvement in cell current to CBA, because moving the CMOS off the array wafer frees the array to use a thermal budget chosen for the cell rather than for the transistors underneath it [13].

**Cost per bit versus layer count.** This is the question that decides whether the race continues. Adding layers raises bits per die, but it also raises process steps, tool time and defect opportunities. Vendors have responded by pushing on two other axes as well. Lam calls them lateral scaling (packing the holes closer together and shrinking the cell) and logical scaling (more bits per cell), alongside vertical scaling [6]. Pletka expected the same: thinner layers, denser hole placement, shared bit lines, split-gate architectures and more bits per cell, keeping density on trend "at least for the next 5 to 10 years" [3].

A concrete example of lateral scaling is the switch of word line metal from tungsten to molybdenum. Tungsten is deposited from a WF6 precursor, and Kioxia found that residual fluorine trapped in voids attacks the cell and inter-word-line dielectrics, causing leakage failures [25]. Molybdenum has lower resistivity and its MoO2Cl2 precursor contains no fluorine. In work with Western Digital presented at the 2024 IEEE Symposium on VLSI Technology and Circuits, Kioxia reported a leakage failure rate a twenty-fifth that of tungsten under horizontal scaling, an 18 percent RC improvement at a 17 percent word line pitch reduction, and a combined XYZ scaling benefit of more than 16.3 percent higher bit density in the same die volume [25][26]. Molybdenum lets the stack get shorter per layer as well as denser, which relieves the etch.

The most direct attack on the etch limit is to stop trying to etch taller stacks at all and bond finished stacks together instead. At the 2026 Symposium on VLSI Technology and Circuits in June 2026, Jeehoon Han of Samsung presented "Demonstration of Cell Multi-Bonding (CMB) Technology for Future Vertical NAND over 1k-Layer," reporting that "for the first time, 900-layer class VNAND integration was implemented by bonding two 450-layer cell wafers" [27]. The abstract is candid about which problems bit: the heavily warped cell wafer had to be held by an appropriately designed upper chuck during bonding, and new overlay correction technology was needed to fix the alignment degradation that warpage caused [27]. This is a research demonstration, not a product, and it should not be read as a shipping capability. It does show where the industry expects the answer to come from, which is the same answer it reached for the periphery: when a single monolithic stack becomes impossible, build the pieces separately and bond them.

## Why the vertical architecture matters for AI infrastructure

Model weights, checkpoints, training corpora and vector indexes live on NAND, and the cost of a bit of NAND is set almost entirely by how many layers a vendor can stack and yield. The AI build-out has made that arithmetic visible: Counterpoint projected in July 2024 that the NAND flash market would more than double from 40 billion dollars in 2023 to 93 billion by 2030, driven by AI servers, AI PCs, AI phones, autonomous vehicles and robotics [5].

The architecture also determines how fast data leaves the die, which is the part that touches accelerator utilisation. Interface speed is a periphery property, and the periphery is exactly what wafer bonding decouples from the memory stack. The progression is visible in the numbers vendors quote: 2.4 GB/s at Micron's 232-layer node in 2022 [9], 3.6 Gbps from Kioxia's first CBA generation [13], 4.8 Gb/s at BiCS10 in 2026 [15]. Lam's framing of the dependency is that the models stored in 3D NAND are loaded into [HBM](/wiki/high_bandwidth_memory) for compute, so the rewrite and reload speed between the two is a function of channel mobility, which is a function of how good the high aspect ratio channel etch was [5]. That is an equipment vendor arguing for its own products, and it should be read as such, but the causal chain from etch profile to model load time is real.

Finally, the vertical architecture is why NAND is the one leading-edge memory that a sanctioned manufacturer can still advance. Density comes from stacking, not from lithography, so extreme ultraviolet tools are not on the critical path. That is the structural reason [YMTC](/wiki/ymtc) has been able to stay within a generation of the leaders on [Chinese](/wiki/china_semiconductor_industry) deposition and etch tools from suppliers such as [AMEC](/wiki/amec) and [NAURA](/wiki/naura), and the reason the same company's move into [DRAM](/wiki/dram) puts it on much harder ground.

## References

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