# AMD Instinct MI430X

> Source: https://aiwiki.ai/wiki/amd_instinct_mi430x
> Updated: 2026-07-27
> Categories: AI Hardware, AI Infrastructure
> License: CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/)
> From AI Wiki (https://aiwiki.ai), the free encyclopedia of artificial intelligence. Reuse freely with attribution to "AI Wiki (aiwiki.ai)".

The **AMD Instinct MI430X** is a data center GPU accelerator built for scientific computing and sovereign AI, and the high-precision member of the [AMD Instinct MI400 series](/wiki/amd_mi400). [AMD](/wiki/amd) first named the part on 2025-10-27, in the announcement that it would power the US Department of Energy's Discovery supercomputer, and published headline specifications and a product page at the Advancing AI 2026 launch event in San Francisco on 2026-07-23 [1][7][2]. AMD states the MI430X reaches up to 288 TFLOPS of peak theoretical hardware-based FP64, paired with 432 GB of [HBM4](/wiki/hbm4) [1][3]. The AI-oriented sibling in the same series, the MI455X, is rated at 5 TFLOPS of FP64 [13]. That roughly 58-to-1 gap inside a single product family is the reason a separate MI430X exists: as accelerator vendors reallocate silicon toward FP4 and FP8 for AI, double precision has stopped being a free byproduct of a big GPU and has become a deliberate, separately provisioned feature. As of 2026-07-27 the MI430X had not shipped, and AMD expects availability in 2027 [1].

## Why a double-precision part still exists

Through the MI300 and MI350 generations, AMD shipped one accelerator that did both jobs. The [MI300X](/wiki/amd_instinct_mi300x) was rated at 81.7 TFLOPS FP64 vector and 163.4 TFLOPS FP64 matrix, and the [MI355X](/wiki/amd_instinct_mi355x) at 78.6 TFLOPS for both [15][14]. A laboratory buying an MI355X for AI training also got a competent double-precision engine, and the same was true of the [MI325X](/wiki/amd_instinct_mi325x) before it.

The MI400 generation breaks that. AMD's published specification table for the MI455X, the part that fills the 72-GPU [Helios](/wiki/amd_helios_rack) rack, lists peak FP64 at 5 TFLOPS for both matrix and vector, against 40.3 PFLOPS of OCP MXFP4 and 20.1 PFLOPS of FP8 [13]. In other words the AI flagship gives up about 94 percent of the previous generation's double-precision throughput to spend the transistors on low-precision matrix work. Simulation codes in climate, fusion, molecular dynamics, computational fluid dynamics, and structural mechanics cannot use FP4, so a machine built from MI455X parts would be close to useless for the DOE and EuroHPC workloads AMD has spent a decade winning.

The MI430X is the answer. AMD describes it as combining "FP64 accuracy for simulation and modeling with modern AI capability for inference, training, and fine-tuning," and pitches it at governments, research institutions, and national laboratories running converged simulation and AI workflows [1]. AMD's framing goes further than tradition: the company argues that high-fidelity FP64 simulation is increasingly the source of training data for scientific AI surrogate models, so numerical accuracy upstream constrains model quality downstream [6][1].

A third series member, the MI440X, was introduced at CES on 2026-01-05 for on-premises enterprise AI in a compact eight-GPU form factor [20]. It does not appear in AMD's July 2026 launch materials or on the MI400 product page, which describe the series as spanning Helios racks of MI455X GPUs and the MI430X for sovereign AI and HPC [4].

## Published specifications

AMD has released far less detail on the MI430X than on the MI455X, which has a full specification table. Board power, process node, form factor, and FP64 matrix throughput were all unpublished as of 2026-07-27.

| Specification | AMD figure |
| --- | --- |
| Peak FP64 (vector) | Up to 288 TFLOPS, peak theoretical, hardware-based [1] |
| Peak FP64 (matrix) | Not published separately |
| Peak FP32 | Not published |
| Peak FP4 / OCP MXFP4 | Up to 9.2 PFLOPS, peak theoretical [1] |
| Peak FP8 | Not published (FP8 support stated) [5] |
| Work Group Processors | 256, Wave32 execution [1] |
| Memory | 432 GB HBM4 [1] |
| Memory bandwidth | Contradictory in AMD materials: 19.6 TB/s, 23.3 TB/s and 2.3 TB/s all appear (see below) |
| Architecture | "Next-generation AMD CDNA"; AMD has not published a CDNA generation number for this SKU [5] |
| Process node | Not published |
| Typical board power | Not published |
| GPU interconnect | Not published; announced systems use HPE Slingshot or Bull BXI at the fabric level [9][10] |
| Form factor and cooling | Not published; announced systems use direct liquid cooling [11] |
| Availability | Expected in 2027 [1] |

Every performance number here is vendor-reported and, per AMD's own endnotes, an engineering projection rather than a measurement on production silicon [1].

The gaps matter. AMD withheld board power across the MI400 series, and independent analysis before the launch put the MI430X in the region of 2,300 W, working from an HPE-stated range of 2,000 W to 2,500 W per GPU, which would be a large jump from the 1,400 W typical board power of the MI355X [19][14]. AMD has not confirmed any figure.

## The comparison claims, and what the endnotes say

AMD's headline competitive claim is that the MI430X has "8.7X better hardware-based FP64 peak FLOP performance over NVIDIA Vera Rubin" [1]. The bar chart accompanying it gives the two numbers: 288 TFLOPS for the MI430X against 33 TFLOPS for [Vera Rubin](/wiki/nvidia_vera_rubin) [1]. The supporting endnote, MI400-001B, describes the basis as "engineering projections by AMD performance labs in July 2026, to estimate peak theoretical precision performance of an AMD Instinct MI430X GPU using FP64 (Vector) datatype vs. NVIDIA Rubin GPU with FP64 (Vector) datatype," with results subject to change at product release [1]. A related endnote, MI400-001C, extends the same comparison to the MI300X and to NVIDIA's B200 and B300 [1]. An earlier version of the claim, published on 2026-05-06 with the projection then standing at "more than 200 TFLOPs" and "more than six times" Rubin, carried endnote MI400-001 and was dated to April 2026 lab projections [6]. Both the figure and the multiple moved upward between May and July 2026.

The words "hardware-based" are doing real work in that sentence. [NVIDIA](/wiki/nvidia) publishes Rubin FP64 vector at 33 TFLOPS, which matches AMD's number, but also publishes 200 TFLOPS of FP64 matrix throughput achieved "using Tensor Core-based emulation algorithms," specifically multi-pass Ozaki-style schemes running over lower-precision tensor cores [17]. NVIDIA's position is that the highest sustained FP64 performance in production simulation codes often comes from matrix-multiply kernels, that emulation can supply those kernels at FP64-level accuracy, and that dedicated FP64 vector hardware only needs to be provisioned well enough to saturate memory bandwidth [17]. AMD's position is that native FP64 silicon is what scientists should be able to trust. Both arguments were on the agenda at the 2026 HPC User Forum, in a panel titled "The Future of Precision in HPC: FP64, Reduced Precision, and Emulation" that AMD joined [6]. On the metric AMD's endnote actually names, FP64 vector against FP64 vector, the comparison is like for like. What the headline leaves out is that Rubin's double-precision story does not end at its vector units: measured against NVIDIA's 200 TFLOPS emulated matrix figure, the multiple would be about 1.4x rather than 8.7x.

The trend data supports AMD's characterization of the direction, at least. NVIDIA's published FP64 vector rates run 34 TFLOPS on Hopper, 40 on [Blackwell](/wiki/nvidia_blackwell), and 33 on Rubin, while FP32 matrix over the same span goes from 67 to 227 to 400 TFLOPS [17]. Double precision has been flat for three generations while everything else grew.

## Memory bandwidth: three different published numbers

AMD's materials do not agree on how fast MI430X memory is. The November 2025 announcement blog states 432 GB of HBM4 and "19.6TB/s of memory bandwidth" [5], AMD's own Alice Recoque press release of 2025-11-18 says each GPU "integrates 432 GB of HBM4 memory and 19.6 TB/s of bandwidth" [10], and HLRS repeats 19.6 TB/s in its own system announcement, presumably from AMD-supplied material [11]. The MI430X product page published in July 2026 shows "Up to 23.3 TB/s Peak Theoretical Memory Bandwidth" in its headline tiles and uses 23.3 TB/s again in a comparison against Vera Rubin's 22.0 TB/s, citing endnote MI400-004 (June 2026 calculations from published specifications) [1]. The FAQ lower down that same page says "432GB of HBM4 and 2.3 TB/s memory bandwidth" [1].

The 23.3 TB/s figure matches the MI455X specification table exactly, which is consistent with the two parts sharing a 12-stack HBM4 subsystem [13]. The 2.3 TB/s figure appears to be a typographical error, since it would be less than half the bandwidth of the three-year-old MI300X [15]. Whether 19.6 TB/s is a superseded early projection or a different binning of the same memory is not something AMD has explained, and it is not purely a 2025 artefact. The MI455X carries the same split in currently live material: its specification table and one FAQ answer on the MI400 series page both give 23.3 TB/s, while the AMD Helios answer on that same page, still published on 2026-07-27, credits each MI455X with "up to 19.6 TB/s bandwidth" [4][13]. This article reports the discrepancy rather than picking one.

## Announced deployments

Three systems have been publicly confirmed by AMD, the operator, or both. AMD's product FAQ names all three [1].

| System | Operator | Confirmed by | Configuration and timing |
| --- | --- | --- | --- |
| Discovery | Oak Ridge National Laboratory (US DOE) | ORNL, HPE and AMD, 2025-10-27 [7][8][9] | HPE Cray Supercomputing GX5000; nodes of 1 next-generation [EPYC "Venice"](/wiki/amd_epyc_venice) CPU and 4 MI430X GPUs; HPE Slingshot interconnect; delivery 2028, user operations 2029 [9][7] |
| Alice Recoque | GENCI and CEA, France, for EuroHPC JU | AMD and Eviden, 2025-11-18 [10] | Eviden BullSequana XH3500 with Venice CPUs and MI430X GPUs, Bull BXI network; targeted at more than one exaflop of HPL; 544 million euro programme [10] |
| Herder | HLRS Stuttgart, Germany | HLRS, 2025-12-02 [11] | HPE Cray GX5000, MI430X plus Venice, HPE Slingshot 400, direct liquid cooling; delivery in the second half of 2027, in service by end of 2027; more than seven times the peak performance of the current Hunter system [11] |

HLRS did not publish an accelerator count. The German technology outlet heise online reported 1,488 MI430X GPUs and 372 Venice CPUs, two CPUs and eight GPUs per board, for roughly 643 TB of HBM4 system-wide [12]. At AMD's published 288 TFLOPS per GPU that count works out to about 428 PFLOPS of peak FP64.

Neither ORNL nor HLRS has published node-level or system-level performance figures. The OLCF system page for Discovery lists node performance and system size as "Not reported at this time" [9]. AMD has separately described Discovery as running under the DOE's Genesis Mission programme [6]. Reports tying MI430X-class parts to other machines circulated during 2026, but only Discovery, Alice Recoque, and Herder are confirmed in primary sources.

## Software support

AMD positions [ROCm](/wiki/rocm) as the MI430X programming stack, offering the same compilers, libraries, and runtimes across HPC and AI, with portability presented as an argument for sovereign operators avoiding vendor lock-in [1]. The announced systems list conventional HPC programming models: MPI, OpenMP, HIP, Kokkos, and RAJA [9].

Public ROCm support does not yet exist. The ROCm 7.14.0 compatibility matrix, last updated 2026-07-16 and still current on 2026-07-27, lists Instinct hardware only through gfx950, meaning MI355X, MI350X, and [MI350P](/wiki/amd_instinct_mi350p), plus the older gfx942, gfx90a, and gfx908 parts [18]. No MI400 series device appears, including the MI455X that AMD put into production the same month. That is normal for a part a year away from availability, but it means no public toolchain targets MI430X silicon today.

## Compared with earlier Instinct accelerators

| Part | FP64 vector | FP64 matrix | Memory | Bandwidth | Board power |
| --- | --- | --- | --- | --- | --- |
| MI300A (2023) | 61.3 TFLOPS | 122.6 TFLOPS | 128 GB HBM3 | 5.3 TB/s | 550 W TDP, 760 W peak [16] |
| [MI300X](/wiki/amd_instinct_mi300x) (2023) | 81.7 TFLOPS | 163.4 TFLOPS | 192 GB HBM3 | 5.3 TB/s | 750 W peak [15] |
| [MI355X](/wiki/amd_instinct_mi355x) (2025) | 78.6 TFLOPS | 78.6 TFLOPS | 288 GB [HBM3E](/wiki/hbm3e) | 8 TB/s | 1,400 W [14] |
| MI455X (2026) | 5 TFLOPS | 5 TFLOPS | 432 GB HBM4 | 23.3 TB/s | Not published [13] |
| MI430X (2027, projected) | 288 TFLOPS | Not published | 432 GB HBM4 | See above | Not published [1] |

Two things stand out. FP64 matrix throughput peaked with the MI300 generation and then collapsed: AMD folded matrix and vector FP64 to the same 78.6 TFLOPS rate on the MI355X, and the MI455X abandoned both. And the MI430X's low-precision rate, 9.2 PFLOPS of MXFP4, is roughly 23 percent of the MI455X's 40.3 PFLOPS, despite the two parts sharing a 256-WGP count and the same memory capacity [1][13]. Whatever AMD changed in the matrix engines to restore double precision appears to have cost most of the FP4 throughput. AMD has not described the microarchitectural difference.

## Availability and independent evaluation

AMD states only that MI430X GPUs are "expected to be available in 2027" and that more details will follow [1]. It has not committed to a half or a quarter. The earliest confirmed customer delivery is Herder in the second half of 2027 [11]; Discovery arrives in 2028 and enters user operations in 2029 [7][9].

No independent benchmark results for the MI430X existed as of 2026-07-27. The part is not in production, has no public ROCm support, has never appeared in an [MLPerf](/wiki/mlperf) submission, and no third party has been given hardware. Every performance number in circulation traces back to AMD engineering projections, and AMD's own cautionary language marks them as forward-looking statements subject to change [6]. Pre-launch third-party estimates, such as the Chips and Cheese analysis that worked backwards from Alice Recoque's exaflop HPL target to roughly 211 TFLOPS of FP64 vector, came in below AMD's eventual 288 TFLOPS claim [19]. Any comparison of the MI430X against Vera Rubin or another accelerator is vendor projection against vendor projection until silicon ships.

## See also

- [AMD Instinct MI400](/wiki/amd_mi400), the series this part belongs to
- [AMD Advancing AI 2026](/wiki/amd_advancing_ai_2026), the launch event
- [AMD Instinct MI455X](/wiki/amd_instinct_mi455x), the AI-focused sibling
- [Sovereign AI](/wiki/sovereign_ai) and [AI for Science](/wiki/ai_for_science), the demand drivers behind these procurements
- [AI accelerator comparison](/wiki/ai_accelerator_comparison)

## References

1. "AMD Instinct MI430X GPUs." AMD, accessed 2026-07-27. https://www.amd.com/en/products/accelerators/instinct/mi400/mi430x.html
2. "AAI 2026: AMD Delivers Full-Stack Compute for the Agentic AI Era." AMD Investor Relations, 2026-07-23. https://ir.amd.com/news-events/press-releases/detail/1294/aai-2026-amd-delivers-full-stack-compute-for-the-agentic-ai-era
3. "AAI 2026: AMD Launches AMD Instinct MI400 Series GPUs for Frontier AI, HPC." AMD Newsroom, 2026-07-23. https://newsroom.amd.com/news/aai-2026-mi400-instinct-update/
4. "AMD Instinct MI400 Series GPUs." AMD, accessed 2026-07-27. https://www.amd.com/en/products/accelerators/instinct/mi400.html
5. "AMD Instinct MI430X: Powering the Next Wave of AI and Scientific Discovery." AMD Blogs, 2025-11-19. https://www.amd.com/en/blogs/2025/amd-instinct-mi430x-powering-the-next-wave-of-ai.html
6. "AMD at the HPC User Forum 2026: AMD sets new bar for HPC with AMD Instinct MI430X GPU FP64 performance." AMD Blogs, 2026-05-06. https://www.amd.com/en/blogs/2026/amd-sets-new-bar-for-hpc-with-amd-instinct-mi430x-gpu.html
7. "AMD Powers U.S. Sovereign AI Factory Supercomputers, Accelerating an Open American AI Stack." AMD Newsroom, 2025-10-27. https://www.amd.com/en/newsroom/press-releases/2025-10-27-amd-powers-u-s-sovereign-ai-factory-supercomputer.html
8. "ORNL, AMD and HPE to deliver DOE's newest AI supercomputers: Discovery and Lux." Oak Ridge National Laboratory, 2025-10-27. https://www.ornl.gov/news/ornl-amd-and-hpe-deliver-does-newest-ai-supercomputers-discovery-and-lux
9. "Discovery." Oak Ridge Leadership Computing Facility, accessed 2026-07-27. https://www.olcf.ornl.gov/olcf-resources/compute-systems/discovery/
10. "AMD and Eviden to Power Europe's New Exascale Supercomputer, the First Based in France." AMD Investor Relations, 2025-11-18. https://ir.amd.com/news-events/press-releases/detail/1267/amd-and-eviden-to-power-europes-new-exascale-supercomputer-the-first-based-in-france
11. "HLRS Announces Details of Herder Supercomputer." High-Performance Computing Center Stuttgart, 2025-12-02. https://www.hlrs.de/news/detail/hlrs-announces-details-of-herder-supercomputer
12. "HLRS Supercomputer Herder to feature CPUs and GPUs from AMD." heise online, 2025-12-02. https://www.heise.de/en/news/HLRS-Supercomputer-Herder-to-feature-CPUs-and-GPUs-from-AMD-11104995.html
13. "AMD Instinct MI455X GPUs." AMD, accessed 2026-07-27. https://www.amd.com/en/products/accelerators/instinct/mi400/mi455x.html
14. "AMD Instinct MI355X Accelerator." AMD, accessed 2026-07-27. https://www.amd.com/en/products/accelerators/instinct/mi350/mi355x.html
15. "AMD Instinct MI300X Accelerator." AMD, accessed 2026-07-27. https://www.amd.com/en/products/accelerators/instinct/mi300/mi300x.html
16. "AMD Instinct MI300A Accelerator." AMD, accessed 2026-07-27. https://www.amd.com/en/products/accelerators/instinct/mi300/mi300a.html
17. "Inside the NVIDIA Vera Rubin Platform: Six New Chips, One AI Supercomputer." NVIDIA Technical Blog, updated 2026-03-16. https://developer.nvidia.com/blog/inside-the-nvidia-rubin-platform-six-new-chips-one-ai-supercomputer/
18. "ROCm 7.14.0 compatibility matrix." AMD ROCm documentation, updated 2026-07-16. https://rocm.docs.amd.com/en/latest/compatibility/compatibility-matrix.html
19. "SC25: Estimating AMD's Upcoming MI430X's FP64 and the Discovery Supercomputer." Chips and Cheese, 2025-12-10. https://chipsandcheese.com/p/sc25-estimating-amds-upcoming-mi430xs
20. "AMD and its Partners Share their Vision for 'AI Everywhere, for Everyone' at CES 2026." AMD Investor Relations, 2026-01-05. https://ir.amd.com/news-events/press-releases/detail/1272/amd-and-its-partners-share-their-vision-for-ai-everywhere-for-everyone-at-ces-2026