# AMD Pensando

> Source: https://aiwiki.ai/wiki/amd_pensando
> Updated: 2026-07-27
> Categories: AI Hardware, AI Infrastructure, Data Centers
> License: CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/)
> From AI Wiki (https://aiwiki.ai), the free encyclopedia of artificial intelligence. Reuse freely with attribution to "AI Wiki (aiwiki.ai)".

AMD Pensando is the data processing unit (DPU) and AI networking product line of [AMD](/wiki/amd), built around Pensando Systems, a startup AMD acquired in 2022 in a transaction valued at approximately $1.9 billion [1]. Pensando was founded in 2017 by a group of former Cisco executives with John Chambers as chairman and investor, and it sold programmable network cards that took software-defined networking, storage and security work off cloud servers [2][3]. Inside AMD, that lineage now supplies three things: the Pensando DPUs that run front-end infrastructure services in [hyperscaler](/wiki/hyperscaler) clouds, the Pollara and Vulcano AI network interface cards that carry traffic between accelerators, and the networking silicon AMD lists in its [Helios](/wiki/amd_helios_rack) rack-scale AI systems [4][5].

## What a DPU is, and why AI clusters want one

A [data center](/wiki/data_center) server does more than run applications. It also encapsulates and routes virtual network traffic, enforces firewall rules and access control lists, terminates encryption, translates addresses, balances load, attaches remote storage, and produces telemetry. Run all of that on the host [CPU](/wiki/cpu) and it competes with the workload the customer is paying for. A DPU is a separate programmable processor, usually on a PCIe card, that executes those infrastructure services at line rate on its own silicon.

The AMD Pensando design does this with a P4-programmable packet pipeline (P4 is a domain-specific language for describing packet processing) plus a cluster of [Arm](/wiki/arm_holdings) cores for control-plane software and fixed-function engines for cryptography, compression, checksums and deduplication [6]. Because the pipeline is programmed rather than hardwired, an operator can add a new encapsulation format or a new telemetry export without waiting for a new chip.

Three properties matter specifically for AI clusters. First, traffic in a training or distributed inference job is overwhelmingly east-west, meaning server to server rather than server to internet, and it is bursty and synchronised: thousands of accelerators finish a step at roughly the same moment and all try to exchange gradients at once. That produces incast congestion which ordinary Ethernet handles poorly, so congestion control and multipathing move into the endpoint. Second, a stalled network idles very expensive [GPUs](/wiki/gpu), so the metric operators care about is job completion time rather than peak link rate [7]. Third, a cloud provider renting bare-metal AI servers still needs tenant isolation and an air gap between the tenant's operating system and the provider's infrastructure. A DPU placed between the host and the switch gives the provider a trusted enforcement point that the tenant cannot reach; IBM Cloud uses AMD Pensando Elba cards this way in its Bare Metal Servers for VPC [8].

AMD Pensando cards support several deployment modes for that reason: host mode, where the card presents virtual functions to the server; bump-in-the-wire mode, where the PCIe slot supplies only power and the card sits inline between the server NIC and the switch with no host driver at all; a pooled appliance mode, where several DPUs serve a group of servers; and NVMe mode, where the card emulates local NVMe devices and terminates NVMe over TCP or RoCE on the far side [14].

## Origins: the MPLS team and Pensando Systems

Pensando's founders, Mario Mazzola, Prem Jain, Luca Cafiero and Soni Jiandani, were known around Cisco as "MPLS," an acronym of their first names that also happens to match a networking protocol [9][10]. At Cisco they drove the company's "spin-in" strategy, in which Cisco was the sole investor in a startup its own veterans founded and then bought the company back once the product existed; Nuova Systems and Insieme Networks came out of that arrangement [9]. All four left Cisco in 2016 after Chuck Robbins replaced John Chambers as chief executive, and founded Pensando in 2017 [9][10]. It was the first venture the group built outside Cisco.

The company left stealth on 2019-10-16 with a Series C of up to $145 million led by Hewlett Packard Enterprise and Lightspeed Venture Partners, with Oracle, Goldman Sachs, NetApp and Equinix also participating, bringing total funding to $278 million after a $71 million founder-led Series A and a $62 million customer-led Series B [2]. By 2022 the total had reached about $313 million, and the company employed roughly 330 people, more than 200 of them in India [9]. John Chambers, by then running JC2 Ventures, was chairman and an investor [3][9]. Prem Jain was chief executive. The pitch was explicitly competitive with Amazon's Nitro system: a distributed services platform that would give any enterprise or non-Amazon cloud the same offload architecture that AWS had built for itself [3].

The first design win visible to the outside world was the HPE Aruba CX 10000, announced on 2021-10-19 and shipping from January 2022. It put two Pensando DPUs inside a top-of-rack switch alongside 48 ports of 10/25G and six 40/100G uplinks, so that firewall, NAT, encryption and telemetry ran at the rack edge instead of on a centralized appliance [11].

## The AMD acquisition

AMD announced a definitive agreement on 2022-04-04 to buy Pensando for approximately $1.9 billion before working capital and other adjustments, and closed the deal on 2022-05-26 [27][1]. The headline price is the transaction value, not the accounting one: AMD's Form 10-Q for that quarter records purchase consideration of $1.7 billion, which is the $1.9 billion less deferred cash compensation requiring future service and other customary closing adjustments, and puts the cash outlay net of cash acquired at $1,558 million. What AMD bought was all issued and outstanding shares of Pensando Systems, Inc., of which $349 million was allocated to acquisition-related intangibles [28]. AMD's stated rationale was that Pensando's DPU and software stack were already deployed at scale, and the release named Goldman Sachs, IBM Cloud, [Microsoft Azure](/wiki/azure) and [Oracle](/wiki/oracle) Cloud as customers [1]. Prem Jain and the Pensando team joined AMD's Data Center Solutions Group under senior vice president and general manager Forrest Norrod [27].

The purchase looks different in hindsight than it did in 2022. It was pitched as a cloud infrastructure play. What it bought AMD, four years later, was a networking team and a programmable packet engine at exactly the moment when rack-scale AI systems made networking a gating factor.

## Product line by generation

AMD numbers the DPUs and the AI NICs separately. The DPU line runs Capri, Elba, Giglio and Salina; the AI NIC line begins with Pollara 400 and continues with Vulcano 800.

| Product | Line and generation | Announced | Line rate | Host interface | Notable specifications |
|---|---|---|---|---|---|
| Capri | DPU, 1st gen | 2019 | 100G | Not published | The original Pensando ASIC, 16 nm per TechInsights [12] |
| Elba | DPU, 2nd gen | Detailed at Hot Chips 32, August 2020 [30] | 2 x 200 Gb/s | 32 lanes PCIe Gen4 | 144 P4 match processing units at 2 GHz; 16 Arm A72 cores at 3 GHz; dual DDR4-3200, 8 GB to 64 GB; 7 nm per TechInsights [6][12] |
| Giglio | DPU, 2nd gen plus | 2023-06-13 roadmap disclosure [29]; product brief April 2024 | 2 x 200 Gb/s | 16 lanes PCIe Gen4 | Same 144 MPU and 16-core A72 architecture as Elba, power and performance optimized, source-code compatible with Capri and Elba [13] |
| Salina (Salina 400) | DPU, 3rd gen | 2024-10-10 | 400 Gb/s throughput; 2 x QSFP112 ports | PCIe Gen5 x16 | 64 GB DDR5-6400 with ECC on the shipping card; RoCEv1/v2; NVMe virtualization and NVMe-oF; AMD claims up to 2x the previous generation [4][14] |
| Pollara 400 | AI NIC, 1st gen | 2024-10-10 | Up to 400 Gbps | PCIe Gen5 x16 | 3rd-generation P4 programmable engine; HHHL and OCP 3.0 TSFF form factors; QSFP112; 25/50/100/200/400 Gbps [14][15] |
| Vulcano 800 | AI NIC, 2nd gen | 2025-06-12 (roadmap), detailed 2026-07-23 | 800 Gbps per NIC | Not published by AMD; ServeTheHome describes it as a NIC for next-generation PCIe Gen6 clusters [16] | Up to 2.4 Tbps of scale-out bandwidth per GPU using three NICs per GPU; multi-plane architecture; supports MRC transport [5][7] |

Two future Pensando generations appear on AMD's July 2026 roadmap but have no published specifications: "Como" and "Monza" networking for the Helios 500 rack, and "Palma" and "Levanzo" for Helios 600 [17].

### Pollara 400 and Ultra Ethernet

Pollara 400 is the part most often cited as AMD's answer to proprietary AI fabrics. AMD announced it on 2024-10-10 alongside Salina, said both were sampling with customers in Q4 2024, and targeted availability in the first half of 2025 [4]. It shipped in 2025, and at Advancing AI on 2025-06-12 AMD described Pollara NICs as already rolling out in hyperscaler deployments such as Oracle Cloud Infrastructure, with broad availability in the second half of 2025 [18].

Precision matters on the [Ultra Ethernet](/wiki/ultra_ethernet) question, because the marketing language has shifted over time. AMD's own product brief calls Pollara 400 "the industry's first Ultra Ethernet Consortium (UEC) ready, fully programmable AI NIC," and lists "UEC Ready RDMA" as a feature [15]. The Ultra Ethernet Consortium published Specification 1.0 on 2025-06-11, roughly eight months after Pollara was announced [19]. The consortium has revised it three times since, to 1.0.1 on 2025-09-05, 1.0.2 on 2026-01-28 and 1.0.3 on 2026-07-16, which is the current published version; UEC publishes compliance checklists and test bed recommendations but no public register of certified products, so "compliant" is a vendor's own assertion rather than a consortium finding [34]. Network World reported in June 2025 that the card was the first NIC compliant with UEC 1.0 [20]. AMD's later phrasing is more cautious: its July 2026 Vulcano blog says only that AMD "was first to market with Ultra Ethernet Consortium (UEC) support in its previous generation of AI NIC" [7]. The practical position is that Pollara implements the UEC transport behaviors (packet spray across multiple paths, out-of-order receive with in-order delivery to the GPU, selective retransmission, path-aware congestion control) in a programmable pipeline that can be updated in firmware as the specification settles, and that it also speaks conventional RoCEv2 for interoperability [15][21].

### Vulcano 800

Vulcano is the second-generation AI NIC and the one AMD ties to Helios. AMD says it delivers 800 Gbps per NIC and up to 2.4 Tbps of scale-out bandwidth per GPU through a configuration of three NICs per GPU, and that it carries MRC (Multipath Reliable Connection), a transport protocol AMD says was co-developed for [OpenAI](/wiki/openai) to meet the reliability and throughput requirements of large-scale training [7]. AMD also positions Vulcano for "scale-across," meaning links between data centers carrying the same latency-sensitive collective traffic that used to stay inside one building [7]. AMD's Vulcano blog does not claim UEC compliance for the part itself; it says only that AMD "was first to market with Ultra Ethernet Consortium (UEC) support in its previous generation of AI NIC" [7]. The joint AMD and Oracle announcement says Vulcano supports advanced RoCE and UEC standards [24], and Network World reported in June 2025, when Vulcano was still a roadmap part, that AMD called it fully UEC 1.0 compliant [20]. As of 2026-07-27 AMD has not published a Vulcano product brief with a full specification table, so the process node, core counts and memory configuration are not public.

## Role in AMD Helios

At Advancing AI 2026 on 2026-07-23, AMD launched [Helios](/wiki/amd_helios_rack), a rack combining 72 Instinct [MI455X](/wiki/amd_mi400) GPUs and 18 6th Gen EPYC ["Venice"](/wiki/amd_epyc_venice) CPUs "connected by AMD Pensando front-end, scale-up and scale-out networking" [17]. AMD splits the networking into three layers:

- **Front end**, handling ingestion, authentication, storage access and traffic security, run by the Pensando Salina DPU. AMD's 2026 framing adds an AI-specific job: the DPU manages NVMe storage so that [KV cache](/wiki/kv_cache) can spill beyond GPU memory and support million-token contexts [5].
- **Scale up**, binding the 72 GPUs into one memory domain, run by UALoE, which is [UALink](/wiki/ualink) tunneled over standard [Ethernet](/wiki/ethernet) switch silicon. AMD states up to 260 TB/s of aggregate scale-up bandwidth and access to 31 TB of HBM4 in a rack, with each GPU connected through 18 independent UALoE stations across separate switch trays so a single failure does not kill the job [22].
- **Scale out and across**, connecting racks and sites, run by the Vulcano 800 AI NIC [5].

Above the hardware sit AMD Fabric Manager and AMD Fabric OS for provisioning, telemetry and fault recovery, plus vPods, which partition the 72-GPU domain into isolated software-defined environments so several workloads can share a rack [22].

## Deployments

| Customer or partner | What is deployed | Source |
|---|---|---|
| Microsoft Azure | Pensando DPUs in AMD AI back-end networking infrastructure and select Azure services; SDN appliances deployed in pairs, six DPUs per appliance, in the Accelerated Connections service; integration with Azure Boost announced 2026-07-20, along with a commitment to deploy Helios | [33][23][5] |
| Oracle Cloud Infrastructure | First cloud provider to deploy Pollara 400 on back-end networks; the OCI supercluster announced 2025-10-14 pairs Instinct MI450 GPUs and EPYC "Venice" with Pensando "Vulcano" networking, up to three 800 Gbps Vulcano NICs per GPU, with an initial deployment of 50,000 GPUs starting in calendar Q3 2026 | [18][20][24] |
| IBM Cloud | Elba DSC2-200 cards in Bare Metal Servers for VPC, running Ubuntu Core, for tenant isolation and infrastructure air gap | [8] |
| HPE Aruba Networking | CX 10000 distributed services switch, two Pensando DPUs per switch | [11] |
| Cisco | N9300 Series Smart Switches, announced 2025-02-11, pairing Cisco Silicon One E100 with AMD Pensando DPUs to host services such as Hypershield in the switch | [25] |
| Goldman Sachs | Named as a Pensando customer at the 2019 launch and again in AMD's 2022 acquisition release | [1][2] |

AMD reports results in Data Center, Client and Gaming, and Embedded segments and does not break out Pensando revenue separately, so the size of the business is not publicly known.

## Competitive position

The DPU and AI NIC market is contested, and the three main players are not structured the same way.

[NVIDIA](/wiki/nvidia) sells both endpoints and switches. Its [BlueField](/wiki/bluefield) DPUs occupy the same slot as Pensando; BlueField-4, announced on 2025-10-28, moves to 800G and pairs an NVIDIA Grace CPU with ConnectX-9 networking for what NVIDIA calls six times the compute of BlueField-3, with 64 Arm cores reported from NVIDIA's presentation slides [31][26]. NVIDIA's wording was that BlueField-4 is "expected to launch in early availability as part of NVIDIA Vera Rubin platforms in 2026," not early 2026, and at CES in January 2026 NVIDIA said BlueField-4 based storage platforms would be available in the second half of 2026 [31][32]. Its [ConnectX](/wiki/connectx) adapters and SuperNICs handle back-end GPU traffic, and its [Spectrum-X](/wiki/nvidia_spectrum_x) Ethernet platform and [InfiniBand](/wiki/infiniband) fabrics supply the switching. That vertical integration is NVIDIA's advantage on tuning and its exposure on lock-in, and AMD's marketing leans hard on the second point [7].

[Broadcom](/wiki/broadcom) dominates merchant switch silicon with the Tomahawk family, including [Tomahawk 6](/wiki/broadcom_tomahawk_6), and also sells the Thor NIC line. AMD does not build switch ASICs at all. Its designs assume merchant switches: AMD's own cost modeling for Pollara and Vulcano is built on Broadcom Tomahawk 5 and Tomahawk 6 platforms [15][7]. So AMD and Broadcom are partly rivals at the NIC and partly co-dependent at the fabric.

Intel is the third historical entrant with its IPU line, though it has been less visible in AI cluster designs than either AMD or NVIDIA.

AMD's structural argument is that an open Ethernet fabric governed by UEC and UALink lets an operator mix vendors and upgrade layers independently, while a proprietary fabric forces whole-fabric decisions [7]. The counterargument, which AMD does not make, is that open standards arrive later and that a single-vendor stack ships tuned software on day one. As of 2026-07-27 neither position has been settled by deployment data that is public.

## Performance claims and what has been independently verified

Almost every published performance figure for AMD Pensando is vendor-reported, and several rest on comparisons that deserve scrutiny.

| Claim | Basis | Status |
|---|---|---|
| Pollara 400 delivers 1.2x the performance of Broadcom Thor2 on a 128-GPU cluster with RoCEv2 collectives | AMD endnote PEN-013 | Vendor-reported |
| UEC-ready RDMA gives about 25% better all-reduce than RoCEv2 | AMD endnote PEN-016: AMD Performance Labs, 2025-04-28, two nodes of 8 MI300X GPUs behind a Broadcom Tomahawk 4 leaf switch, all-reduce at 4 queue pairs, averaged over message sizes from 512 MB to 16 GB | Vendor-reported, small test bed |
| Salina DPU delivers up to 1.4x NVIDIA BlueField-3 | AMD endnote PEN-017: AMD Performance Labs measured an average of 117 million packets per second on 2025-04-15; the BlueField-3 figure of 80 Mpps comes from NVIDIA's Hot Chips 2021 slide 6 | Vendor-reported, and the bases do not match. NVIDIA's 80 Mpps is the "2x40M PPS at scale of millions of flows" line on a slide whose headline rate is 2x370M PPS, while AMD does not state the flow scale behind its own 117 Mpps [35] |
| Vulcano 800 gives up to 13% faster AI job completion | AMD silicon modeling and synthetic simulation of 8,000 MI455X GPUs, comparing three Vulcano NICs per GPU against two | Simulation, not measurement; AMD's own footnote says results assume ideal behavior |
| Vulcano 800 cuts switching cost by up to 33% | AMD endnote PEN-022: pricing model dated 2026-05-18 for a 32,000-GPU fabric, using SemiAnalysis hyperscaler networking pricing data | Vendor-modeled, and broader than the headline word "switching" suggests. The endnote's own totals are $124M of fabric capex for the competing design against $93M for the Vulcano design, a $30.7M gap that includes optics and cables. That is 33% of the Vulcano design's cost but about 25% of the competitor's; switching hardware alone is $60M against $50M |

Sources: AMD product brief endnotes and AMD's July 2026 networking blogs [15][5][7].

The closest thing to third-party validation published so far is joint work by Cisco and AMD. On 2026-05-07 Cisco published results from two Clos topologies built with Cisco N9364E-SG2 switches, 128 [MI300X](/wiki/amd_instinct_mi300x) GPUs and 128 Pollara 400 NICs, measured with IBPerf and [MLPerf](/wiki/mlperf), reporting that P01 and P99 bandwidth stayed close to the 400 Gbps link rate even under a 31:1 incast pattern with 3,968 simultaneous RDMA sessions, and referencing [G42](/wiki/g42) deployments [21]. That is a partner test rather than an independent one. No fully independent benchmark comparing Pollara or Vulcano against competing NICs had been published as of 2026-07-27.

## Strategic significance

The point is narrower than "networking is important." At rack scale, a training step or a distributed [inference](/wiki/inference) request does not finish until the slowest collective operation finishes, so an accelerator's utilization is set by the fabric rather than by its own peak throughput. AMD's own 2026 framing puts it plainly: multi-node training and distributed inference are standard practice, and GPUs stall waiting on data in fabrics that were not designed for them [7]. That is why an accelerator vendor now needs a networking answer, and why NVIDIA sells DPUs, NICs and switches alongside its GPUs. Buying Pensando in 2022 gave AMD an in-house programmable packet engine and, more usefully, an engineering team fluent in transport protocols, four years before Helios shipped. Whether that converts into share against a vertically integrated competitor is unresolved, and the deployment figures that would answer it are not public.

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