# AMD Ryzen AI Embedded X100

> Source: https://aiwiki.ai/wiki/amd_ryzen_ai_embedded_x100
> Updated: 2026-07-27
> Categories: AI Hardware, Embodied AI, Robotics
> License: CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/)
> From AI Wiki (https://aiwiki.ai), the free encyclopedia of artificial intelligence. Reuse freely with attribution to "AI Wiki (aiwiki.ai)".

The **AMD Ryzen AI Embedded X100 Series** is a line of embedded x86 system-on-chip processors announced by [AMD](/wiki/amd) on 2026-07-23 at the company's [Advancing AI 2026](/wiki/amd_advancing_ai_2026) conference in San Francisco, aimed at [robotics](/wiki/robotics), industrial automation, medical imaging, aerospace and defense, and other [physical AI](/wiki/physical_ai) systems that must sense, reason and act under real-time deadlines.[1] Six parts make up the family: the X199, X188 and X168, plus industrial-temperature X199i, X188i and X168i variants. Each combines up to 16 "Zen 5" CPU cores, an integrated RDNA 3.5 GPU with up to 40 compute units, and an XDNA 2 [neural processing unit](/wiki/npu) rated at 50 TOPS, all sharing a single unified memory pool.[2] The silicon is the embedded derivative of AMD's "Strix Halo" client design, the same die family sold to consumers as Ryzen AI Max.[10] Customer sampling began in June 2026 and AMD expects production availability in the fourth quarter of 2026.[1]

The X100 was first named on 2026-01-05, when AMD introduced the Ryzen AI Embedded portfolio and shipped the lower-power P100 Series, then 4 and 6 core parts in a 15 W to 54 W range, while describing the X100 only as a higher-core-count, higher-TOPS sibling for "more demanding physical AI and autonomous systems."[12] AMD extended the P100 line to 8 and 12 cores on 2026-03-09.[14] The July 2026 announcement filled in the X100 specifications.

## Product lineup

All six SKUs share the same memory subsystem, I/O complement, NPU throughput and 55 W nominal TDP. They differ in CPU core count, L3 cache, GPU compute units and junction temperature rating. The "i" suffix denotes the industrial-temperature grade.[2]

| Specification | X168 | X188 | X199 | X168i | X188i | X199i |
| --- | --- | --- | --- | --- | --- | --- |
| "Zen 5" cores / threads | 8 / 16 | 12 / 24 | 16 / 32 | 8 / 16 | 12 / 24 | 16 / 32 |
| CPU max frequency | 5.0 GHz | 5.0 GHz | 5.1 GHz | 5.0 GHz | 5.0 GHz | 5.1 GHz |
| L3 shared cache | 32 MB | 64 MB | 64 MB | 32 MB | 64 MB | 64 MB |
| GPU compute units (RDNA 3.5) | 32 | 32 | 40 | 32 | 32 | 40 |
| GPU max frequency | 2.8 GHz | 2.8 GHz | 2.9 GHz | 2.8 GHz | 2.8 GHz | 2.9 GHz |
| NPU (XDNA 2) | 50 TOPS | 50 TOPS | 50 TOPS | 50 TOPS | 50 TOPS | 50 TOPS |
| Nominal TDP | 55 W | 55 W | 55 W | 55 W | 55 W | 55 W |
| Configurable TDP range | 45-120 W | 45-120 W | 45-120 W | 45-120 W | 45-120 W | 45-120 W |
| Junction temperature | 0 to 105 C | 0 to 105 C | 0 to 105 C | -40 to 105 C | -40 to 105 C | -40 to 105 C |

AMD's product brief lists the X188i at 32 MB of L3, which would make it the only specification where an industrial part differed from its commercial twin. AMD's own per-SKU product specification page for the X188i gives 64 MB, matching the X188, so the 32 MB entry appears to be a typographical error in the brief rather than a real difference.[2][13]

Common to the whole family: a 256-bit LPDDR5x interface running at 8533 MT/s with Link-ECC, giving up to 273 GB/s of memory bandwidth and supporting up to 128 GB of external memory; a 32 MB MALL (memory-attached last level) cache; 16 lanes of PCIe Gen4; two USB4 ports, two USB 3.2 and three USB 2.0; and up to five display outputs across eDP, DisplayPort (listed as 2.1 in the product brief and 2.0 on the per-SKU specification pages), HDMI 2.1, DVI and USB4, driving four displays. The product brief's table lists the 8K mode at 120 Hz, but AMD's launch blog and its per-SKU specification pages both cap a single display at 7680x4320 at 60 Hz.[3][13] Low-speed interfaces cover I2C, SMBus, SPI and UART. The package measures 37.5 mm by 45 mm.[2][8] AMD quotes the X199 at up to 29.7 TFLOPS of FP32 throughput for digital signal processing work accelerated through [ROCm](/wiki/rocm) math libraries.[2]

Consolidating CPU, GPU and NPU on one die is the same [edge AI](/wiki/edge_ai) argument AMD makes for its client parts, but the embedded framing shifts the emphasis from peak inference throughput to how much of a whole [embodied AI](/wiki/embodied_ai) application a single device can absorb, including the graphics, networking, control and orchestration work that never runs on an accelerator.[3]

## Unified memory and why it matters for robots

The architectural argument AMD makes for the X100 is not TOPS but memory. CPU, GPU and NPU address one physical memory pool, which the company describes as a "unified, zero-copy memory architecture."[2] In a conventional robot design, a host CPU and a discrete accelerator each own their own memory, and a perception-to-planning pipeline pays a copy at every handoff: camera and LiDAR frames into the accelerator, feature tensors back out, [sensor fusion](/wiki/sensor_fusion) results back in. Those copies cost both latency and jitter, and jitter is what breaks a control loop.

Sharing memory removes the copies and, AMD argues, makes end-to-end timing more predictable.[4] The Robot Report, covering the launch, framed the same point from the robot builder's side: the X100 "explicitly reduces data copies," which matters most for perception, sensor fusion and planning stages that are tightly coupled.[7]

AMD pairs that with two real-time paths. A "firm real-time" configuration uses BIOS and Linux tuning to target interrupt latency under 7 microseconds at six-nines reliability, backed by AMD QoS features for L3 cache reservation, memory bandwidth allocation and thread isolation. A "hard real-time" configuration runs a Xen-based hypervisor with a FreeRTOS guest, cache coloring and VM isolation.[7] AMD also stresses that all cores are uniform high-performance "Zen 5" cores with AVX-512 across the complex, in contrast to hybrid performance-and-efficiency core designs, which it argues introduce scheduling nondeterminism in real-time systems.[3]

## Performance claims and how AMD measured them

Every performance figure AMD published for the X100 at launch is vendor-reported, and nearly all of them share one methodological caveat that AMD states in its own endnotes: they were not measured on X100 silicon. AMD ran a Ryzen AI Max+ 395 client processor "configured to reflect Ryzen AI Embedded X199 specifications" as a proxy.[2][3] The one exception AMD names is the figure it published with the Kria launch, 8,000 control decisions per second on a 125 microsecond loop, which its endnote says was "obtained by running Bosch Rexroth controller on AMD X100 Series."[9] Tom's Hardware flagged the same issue in its coverage, noting that "there's some sort of proxy stand-in or extrapolation of data across all of the benchmarks here."[10]

| Claim | Comparison target | Method and endnote |
| --- | --- | --- |
| Up to 2.1x multithread CPU | Intel Core Ultra X7 358H | CoreMark v1.01, Ubuntu 24.04; AMD measured at 45 W, Intel measured at 30 W and projected to 45 W (REX-007)[3] |
| 1.7x graphics (OpenGL) | Intel Core Ultra X7 358H | GFXBench 5.0.0 offscreen geomean, same power projection (REX-003)[3] |
| 1.4x graphics (Vulkan) | Intel Core Ultra X7 358H | GFXBench 5.0.0 offscreen geomean (REX-002)[3] |
| 3.5x token generation, 1.4x faster time-to-first-token | Intel Core Ultra X7 358H | llama-bench Vulkan build across six quantized models including [Gemma 4](/wiki/gemma_4) 26B.A4B and Llama 3.1 8B, all fitting under 24 GB (REX-017)[3] |
| 1.3x higher sustained memory bandwidth | Intel Core Ultra Series 3 | STREAM geomean (REX-009)[3] |
| 1.3x throughput on frontier and foundational [VLA models](/wiki/vision_language_action_model) | NVIDIA Jetson AGX Orin 64 GB at 60 W | Geomean over [GR00T N1.5](/wiki/groot_n1_5), [SmolVLA](/wiki/smolvla), [Pi0](/wiki/pi_0_5) DROID, Pi0.5 DROID and [OpenVLA](/wiki/openvla) at FP16 (REX-001)[5] |
| 1.7x faster ultrasound beamforming | Ryzen 7 9800X3D plus discrete NVIDIA RTX 4000 SFF Ada | 128-channel planewave scans, RF copy to display, Vulkan (REX-015)[1] |
| ~$3,000 system cost saving | NVIDIA Jetson AGX Orin Industrial module | AMD analysis against a $3,199 public module price as of 2026-07-06 (REX-013)[3] |
| Up to 3x peak FP32 | NVIDIA Jetson T5000 | No endnote published |

Two caveats deserve emphasis. First, the Intel comparisons rest on measured AMD results at 45 W versus Intel results measured at 30 W and then scaled up to 45 W "using scaling factors derived from public benchmark data for the 358H."[3] AMD never ran the Intel part at the power level it reports. Second, AMD compares against one specific Intel SKU, the Core Ultra X7 358H, while headlining the family name "Intel Core Ultra Series 3."

### The FP32 comparison against Jetson Thor

AMD's most-quoted robotics claim, "up to 3x higher peak FP32 performance compared to Nvidia Jetson T5000," appears in the press release, the product page and the technical blog, and in none of the three does it carry an endnote.[1][3][5] The other performance figures on those same pages are footnoted with test configurations; this one is not. It is a peak theoretical arithmetic rate, not a measured workload result, and AMD does not publish the Jetson figure it is comparing its own 29.7 TFLOPS against.

Peak FP32 is also a poor proxy for robotics inference. Deployed [inference](/wiki/inference) on edge parts overwhelmingly runs at INT8, FP8 or FP4 on dedicated matrix hardware, not at FP32 on the shader array. NVIDIA's own headline number for the [Jetson AGX Thor](/wiki/jetson_thor) T5000 is 2070 TFLOPS at FP4 with sparsity, or 1035 TFLOPS dense FP4, a metric FP32 comparisons do not touch.[11] AMD is reasonably transparent about the scope: the claim is made in the context of aerospace and defense signal processing, where FP32 genuinely is the working precision. Rob Bauer, senior manager of product management and marketing for AMD's x86 embedded APU portfolio, put it as delivering "three times the FP32 compute performance relative to NVIDIA Thor" for that market, adding that NVIDIA's part is "pretty highly optimized around inferencing in that architecture."[7] Read as an AI-performance claim it is misleading; read as a DSP claim about radar, beamforming and sensor front-ends it is on point.

### The OpenNav benchmark

The one launch-day result not produced inside AMD came from Open Navigation LLC, the organization behind the Nav2 navigation stack for the [Robot Operating System](/wiki/robot_operating_system). AMD commissioned the OpenNav Robotics Workload Benchmark, which Open Navigation published on 2026-07-23; the organization states the work "was a collaboration with AMD, however the benchmark was designed to be reproducible on any platform and executed independently without influence," and released the harness on GitHub.[6]

The benchmark simulates an autonomous forklift moving pallets through a 180,000 square foot warehouse, running localization, perception, global and trajectory planning, collision monitoring and behavior-tree autonomy continuously while a [Gemma 4](/wiki/gemma_4) 31B vision-language model interprets an RGB stream in parallel. Three platforms were compared: an AMD Strix Halo system standing in for the X100 at 120 W, an NVIDIA Jetson Thor at 130 W, and an NVIDIA Jetson AGX Orin at 65 W.[6]

| Metric | Strix Halo (X100 proxy) | Jetson Thor | Jetson AGX Orin |
| --- | --- | --- | --- |
| Missions completed in 15 minutes | 10 of 10 | 10 of 10 | 3 of 10 |
| Control-loop scheduling misses per second | 0.45 | 1.6 | 5.8 |
| Mean CPU utilization (headroom left) | 18.1% (about 82%) | 49.8% (about 50%) | 93.6% (none usable) |
| VLM queries completed | 34 of 47 | 25 of 35 | 0 |

Open Navigation's own conclusions are more balanced than AMD's marketing. It found GPU and memory capability "effectively a tie" between Strix Halo and Thor, with the VLM results within 5% once normalized for power, and judged Thor "very much still up to the task if additional workloads are minimal." The separation is on the CPU side: Strix Halo ran at 18.1% mean CPU utilization against Thor's 49.8%, which Open Navigation described as roughly 1.6x the headroom by utilization and nearly 3x more available CPU cores. Open Navigation also noted that NVIDIA ships "a variety of accelerated software available through the Isaac SDK which AMD does not have parity to as of the time of writing," and that both platforms could be improved by setting thread priorities for the trajectory planners.[6] AMD's derived figures from this run, 3.4x better real-time reliability and 1.6x more free CPU cores, are endnoted REX-018 and REX-016 and were measured on a GMKtec EVO-X2 mini PC, not on X100 hardware. Those endnotes also record that the proxy ran LPDDR5X-7500 memory at a 120 W TDP, so its memory bandwidth sits about 12 percent below the LPDDR5x-8533 of the shipping part while its power budget sits well above the 55 W nominal TDP.[9]

As of 2026-07-27, no independent benchmarking of production X100 silicon had been published. The parts were sampling, not shipping.

## Industrial qualification and lifecycle

The industrial SKUs are rated for a junction temperature range of -40 C to 105 C; the commercial parts start at 0 C.[2] AMD lists two reliability grades, a 2.5-year standard mode and an extended mode supporting continuous 24/7 operation for up to 10 years, and states a 10-year production lifecycle with 10-year planned manufacturing availability.[2][3] AMD's per-SKU product specification pages give a last time buy year of 2037 for all six parts, consistent with CNX Software's report that they will remain available for purchase at least until then.[8][13]

AMD contrasts these figures with NVIDIA's specifications for the Jetson T5000, which it says covers five years of continuous operation and a -25 C to 80 C maximum operating range.[4] The two temperature figures are not measured in the same place. AMD's is a junction temperature, taken at the die; the range AMD attributes to NVIDIA is a thermal transfer plate rating, taken at the cooling surface, which runs cooler than the die. NVIDIA's Jetson Thor product page publishes neither an operating temperature range nor a continuous-operation lifetime, so both figures rest on AMD's characterization.[4][15] Module vendors apply their own, tighter limits: congatec's COM-HPC Client Size C modules based on the X100 are rated -40 C to +85 C at the module level.[5]

## Software

AMD is positioning software openness as the main lever against NVIDIA's [CUDA](/wiki/cuda) ecosystem. The stack spans EDKII firmware, Linux with a real-time kernel, the Xen hypervisor, ROS 2, ROCm, Ryzen AI Software, and the standard frameworks [PyTorch](/wiki/pytorch), ONNX and TensorFlow.[2] The AMD Robotics Software Suite, described as a fully open stack built on ROCm and ROS 2, ships accelerated ROS libraries, virtualization and real-time support, reference designs and optimized models.[5][9]

Migration from CUDA runs through HIP and the HIPIFY translator. AMD reports that HIPIFY preserved an average of 83% of CUDA source across foundational GPU workloads, 71% across compute-intensive applications and 72% across AI and machine-learning workloads in a 15-application, 1,199-line validation suite (REX-020), and 81% of a 659-line phased-array beamforming application (REX-021).[3] Those are AMD-internal measurements of source-line retention, not of post-port performance.

## Competitive position

The X100 lands in a segment NVIDIA has dominated. The Jetson AGX Thor T5000, launched in 2025, pairs 14 Arm Neoverse-V3AE cores with a Blackwell GPU of 2560 CUDA cores and 96 tensor cores, 128 GB of LPDDR5X on a 256-bit bus at 273 GB/s, and a 40 W to 130 W configurable envelope.[11] The memory bandwidth is identical to the X100's, and Open Navigation measured GPU capability as roughly equal. The real differences are the CPU (16 x86 cores with SMT and AVX-512 against 14 Arm cores without SMT and with 128-bit Neon vectors), the software ecosystem (where NVIDIA leads), and the industrial lifecycle terms (where AMD leads).[4][6] NVIDIA also broadened the line eight days before the X100 launch, announcing the smaller Thor-architecture T3000 (865 FP4 teraflops) and T2000 (400 FP4 teraflops, 16 GB) modules on 2026-07-15 for availability in the first quarter of 2027.[16]

On the Intel side, [Intel](/wiki/intel) launched Panther Lake SoCs for physical AI earlier in 2026; Tom's Hardware characterized the X100 as physically larger and carrying more silicon for higher-power deployments.[10] Within AMD's own portfolio the X100 sits above the P100 Series, which shares the Zen 5, RDNA 3.5 and 50-TOPS XDNA 2 building blocks at 4 to 12 cores and 15 W to 54 W, and below the [Instinct](/wiki/amd_mi400) data center line.[12][14] The practical target is the class of robot that today pairs a Jetson module with a separate x86 host, a pattern Open Navigation explicitly identified as common and as the strongest case for consolidating on a single APU.[6]

## Availability and partners

Sampling began in June 2026, with production expected in the fourth quarter of 2026.[1] AMD has not published processor pricing. System-on-module launch partners are Arbor, Congatec, iBase, IEI, Sapphire and Seavo; Kontron has announced motherboard support.[1][5] IEI's NANO-X100 board targets semiconductor-fab [autonomous mobile robots](/wiki/autonomous_mobile_robot) in collaboration with CASTEC.[5]

AMD's own [Kria](/wiki/amd_kria) AI SOM is a COM-HPC form-factor module carrying a 16-core X199 with 64 GB or 128 GB of unified memory, sold alongside the Kria AI Robotics Developer Platform, which adds a Spartan UltraScale+ FPGA carrier for real-time I/O and safety functions. AMD expects the SOM from ODM partners in the fourth quarter of 2026; the developer platform was sampling with early-access customers at announcement and is targeted for general availability in the same quarter.[9][8] Early named X100 customers include Castec International, for a semiconductor-fab AMR, and [Foundation Robotics](/wiki/foundation_robotics), a [humanoid robot](/wiki/humanoid_robot) developer migrating from Intel and NVIDIA silicon.[7] Software and ecosystem partners announced with the platform include Open Robotics, Open Navigation and OpenCV.[7] Application areas AMD names beyond robotics are industrial PCs and machine vision, [surgical robotics](/wiki/surgical_robot) and diagnostic imaging, unmanned systems and sensor signal processing, broadcast and pro AV, and casino gaming machines.[2]

## References

1. "AAI 2026: AMD Delivers Leadership Heterogeneous Compute for Physical AI." AMD Newsroom, 2026-07-23. https://newsroom.amd.com/news/aai-2026-ryzen-ai-embedded-x100/
2. "Product Brief: AMD Ryzen AI Embedded X100 Series Processors." AMD, 2026. https://www.amd.com/content/dam/amd/en/documents/products/embedded/ryzen/ryzen-ai-embedded-x100-series-product-brief.pdf
3. Quenton Hall. "AMD Ryzen AI Embedded X100 Series: Consolidating Compute, Graphics and AI at the Edge." AMD Blogs, 2026-07-23. https://www.amd.com/en/blogs/2026/amd-ryzen-ai-embedded-x100-series-consolidating-compute.html
4. Quenton Hall. "From Benchmarks to Behavior: Rethinking Performance in Autonomous Robotics." AMD Blogs, 2026-07-23. https://www.amd.com/en/blogs/2026/from-benchmarks-to-behavior-rethinking-performance-in-a.html
5. "AMD Ryzen AI Embedded X100 Series Processors." AMD product page, 2026. https://www.amd.com/en/products/embedded/ryzen-ai/x100-series.html
6. "AMD Strix Halo vs. NVIDIA Jetson Thor, Orin AGX for Real Robotics Workloads." Open Navigation LLC, 2026-07-23. https://opennav.org/news/opennav-robotics-workload-benchmark
7. "AMD unveils Kria module for real-time control, unified memory for robots." The Robot Report, 2026-07-23. https://www.therobotreport.com/amd-unveils-kria-module-real-time-control-unified-memory-robots/
8. Jean-Luc Aufranc. "AMD launches Ryzen AI Embedded X100 processors, Kria AI SoM, and physical AI/robotics developer platform." CNX Software, 2026-07-24. https://www.cnx-software.com/2026/07/24/amd-launches-ryzen-ai-embedded-x100-processors-kria-ai-som-and-physical-ai-robotics-developer-platform/
9. "AAI 2026: AMD Introduces Open, Turnkey Integrated Platform for Physical AI." AMD Newsroom, 2026-07-23. https://newsroom.amd.com/news/aai-2026-kria-robotics-dev-platform/
10. "AMD's new X100 chip lineup puts embedded Ryzen AI 'Strix Halo' chips into robots." Tom's Hardware, 2026-07-23. https://www.tomshardware.com/pc-components/cpus/amds-new-x100-chip-lineup-puts-strix-halo-into-robots-apus-for-physical-ai-bring-zen-5-cpu-rdna-3-5-gpu-cores-to-compete-with-intels-panther-lake
11. "Introducing NVIDIA Jetson Thor, the Ultimate Platform for Physical AI." NVIDIA Technical Blog, 2025-08-25. https://developer.nvidia.com/blog/introducing-nvidia-jetson-thor-the-ultimate-platform-for-physical-ai/
12. "AMD Introduces Ryzen AI Embedded Processor Portfolio Powering AI-Driven Immersive Experiences in Automotive, Industrial and Physical AI." AMD Newsroom, 2026-01-05. https://www.amd.com/en/newsroom/press-releases/2026-1-5-amd-introduces-ryzen-ai-embedded-processor-portfol.html
13. "AMD Ryzen AI Embedded X188i." AMD product specifications, retrieved 2026-07-27. https://www.amd.com/en/products/embedded/ryzen-ai/x100-series/ryzen-ai-embedded-x188i.html
14. "AMD Expands Ryzen AI Embedded P100 for Edge AI." AMD Blogs, 2026-03-09. https://www.amd.com/en/blogs/2026/amd-expands-ryzen-ai-embedded-p100-for-edge-ai.html
15. "NVIDIA Jetson AGX Thor." NVIDIA product page, retrieved 2026-07-27. https://www.nvidia.com/en-us/autonomous-machines/embedded-systems/jetson-thor/
16. Chen Su. "NVIDIA Introduces New Jetson Thor Computers to Advance Mainstream Robotics and Edge AI." NVIDIA Blog, 2026-07-15. https://blogs.nvidia.com/blog/jetson-thor-robotics-edge-ai-agent/