# Huawei Ascend

> Source: https://aiwiki.ai/wiki/huawei_ascend
> Updated: 2026-08-01
> Fact-checked: 2026-07-24
> Categories: AI Hardware, AI Infrastructure, Chinese AI
> License: CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/) - attribute to "AI Wiki (aiwiki.ai)"
> Cite as: AI Wiki. "Huawei Ascend." aiwiki.ai, 1 Aug 2026. https://aiwiki.ai/wiki/huawei_ascend
> From AI Wiki (https://aiwiki.ai), the free encyclopedia of artificial intelligence. Reuse freely with attribution.

Huawei Ascend is a family of AI accelerators designed by [Huawei](https://aiwiki.ai/wiki/huawei) around a custom processor architecture called Da Vinci. The line runs from low-power inference parts for cameras and edge boxes up to data center training processors and the rack-scale systems assembled from them. Huawei announced the series and the Ascend 910's planned specifications at HUAWEI CONNECT in October 2018, presented the Ascend 310 inference chip publicly weeks later, and formally launched the Ascend 910 in August 2019 [2][3][21].

Ascend matters well beyond Huawei's own balance sheet because it became the default domestic substitute for restricted [NVIDIA](https://aiwiki.ai/wiki/nvidia) hardware inside China. Every major US export control action against Huawei since 2019 has shaped what the chips can be built from and who may legally handle them, and the US Bureau of Industry and Security now names three Ascend part numbers directly in guidance warning that using them risks enforcement action [4][5][6]. The chips are also why Chinese labs such as [iFlytek](https://aiwiki.ai/wiki/iflytek) and Huawei's own [Pangu](https://aiwiki.ai/wiki/pangu) group can claim large-scale model training without American silicon [7][8].

The name covers three layers: the Ascend processors themselves, the Atlas systems that package them (including the [CloudMatrix 384](https://aiwiki.ai/wiki/huawei_cloudmatrix_384) supernode), and the software needed to program them, principally the [CANN](https://aiwiki.ai/wiki/cann) toolkit and the [MindSpore](https://aiwiki.ai/wiki/mindspore) framework.

## Da Vinci, the architecture underneath

Every Ascend part uses the same core design, presented publicly by Heng Liao and colleagues at Hot Chips 31 in August 2019 and later published as an industry-track paper at HPCA 2021 [1][9]. A Da Vinci core combines three compute units: a 1D scalar unit for control flow, a 2D vector unit, and a 3D matrix unit that Huawei calls the cube. The full-size cube is a 16 by 16 by 16 structure holding 4,096 FP16 multiply-accumulate units plus 8,192 INT8 units, with a 2,048-bit vector unit alongside it [1].

The stated reason for the cube shape is arithmetic intensity. Compute in an N-by-N-by-N structure scales as N cubed while data movement scales as N squared, so a larger cube extracts more work per byte fetched. Huawei's own slide compared a 12nm-normalized GPU tensor core block at 5.2 mm2 and 1.7 TOPS of FP16 throughput against a Da Vinci AI core plus SRAM at 13.2 mm2 and 8 TOPS, using Huawei's labelling [1]. The design leans on an explicitly managed memory hierarchy rather than caches: L0 A and B buffers of 64 KB each feed the cube, a 256 KB L0 C buffer collects accumulator output, a 256 KB unified buffer serves the vector unit, and a 1 MB L1 buffer sits above them, all moved by a dedicated memory transfer engine [1].

The same core scales into three configurations, which is how one architecture covers wearables and data centers. Da Vinci Max issues 8,192 cube operations per cycle, Da Vinci Lite 4,096, and Da Vinci Tiny 512 [1]. Huawei used a parallel naming scheme for the chips themselves, labelling the Ascend 310 as Ascend-Mini and the Ascend 910 as Ascend-Max [1]. Da Vinci cores also appear as [NPU](https://aiwiki.ai/wiki/npu) blocks inside Huawei's mobile application processors, automotive SoCs, and wireless SoCs [1].

## Ascend 310 and edge inference

Huawei presented the Ascend 310 at the Fifth World Internet Conference in Wuzhen on 7 November 2018, where board director Yan Lida called it "the first chip in the Ascend series, which opens a new era of AI" [2]. It delivers 16 TOPS at INT8 and 8 TFLOPS at FP16 in an 8 W envelope on a 12nm process, built from two Da Vinci AI cores alongside an eight-core Arm Cortex-A55 cluster, an 8 MB on-chip buffer, a 3 MB last-level cache, and hardware for 16 channels of H.264/H.265 video decode [1][2]. That mix of video decode and modest matrix throughput made it a surveillance and edge analytics part first.

The [inference](https://aiwiki.ai/wiki/inference) tier has continued under the Atlas brand. Huawei said in September 2025 that Ascend supported more than 200 hardware products built on open modules and PCIe cards, with an Atlas 350 card and an Atlas 550 module announced for the following year, so that partners could assemble their own Ascend servers [24]. The wider Atlas family spans accelerator cards, edge boxes, rack servers, and full training clusters, all sharing the CANN software stack.

## Ascend 910 and the 2019 launch

Huawei launched the Ascend 910 in Shenzhen on 23 August 2019, with rotating chairman Eric Xu saying, "We promised a full-stack, all-scenario AI portfolio. And today we delivered." [3] The announced figures were 256 TFLOPS at FP16 and 512 TOPS at INT8, at a maximum power draw of 310 W rather than the 350 W originally planned [3]. The Hot Chips deck describes a 7nm-plus EUV compute die codenamed Vitruvian, 456 mm2 in area, carrying 32 Da Vinci cores, a 32 MB on-chip buffer, and HBM 2.0 interfaces. It is co-packaged with a 168 mm2 I/O die Huawei called Nimbus V3, four HBM stacks, and two dummy dies added for mechanical uniformity, for 1,228 mm2 of silicon in total [1].

Peak-performance figures for the Ascend 910 are not consistent across sources. Huawei's launch release gives 256 TFLOPS FP16, while a 2024 analysis by Jacob Feldgoise and Hanna Dohmen at Georgetown's Center for Security and Emerging Technology (CSET) lists 320 FP16 TFLOPS for the same generation [3][10]. Both figures circulate, and neither should be treated as a precise per-part specification.

Huawei's benchmark claim at launch was that the Ascend 910 paired with MindSpore trained models on [ResNet](https://aiwiki.ai/wiki/resnet)-50 about twice as fast as other mainstream training cards running TensorFlow [3]. A month later, at HUAWEI CONNECT 2019, deputy chairman Ken Hu introduced the Atlas 900 cluster, which Huawei described as combining the power of thousands of Ascend processors, and said it completed ResNet-50 training in 59.8 seconds, 10 seconds faster than the previous world record [11].

## Export controls and the manufacturing problem

The Ascend line's technical history is inseparable from US trade policy. On 16 May 2019 the Bureau of Industry and Security added Huawei Technologies and 68 non-US affiliates, including HiSilicon, to the [Entity List](https://aiwiki.ai/wiki/entity_list) with a presumption of denial for all items subject to the Export Administration Regulations, citing a superseding indictment over unlicensed exports to Iran [4]. That action alone did not stop chip fabrication abroad.

Two 2020 rules did. An interim final rule effective 15 May 2020 attached a foreign-produced direct product rule to Huawei's Entity List entries, and a further rule effective 17 August 2020 added 38 more affiliates and broadened the rule to cover foreign-made items whenever a listed Huawei entity is a party to the transaction as purchaser, consignee, or end user [5]. [TSMC](https://aiwiki.ai/wiki/tsmc), which had fabricated the original Ascend 910, has said it halted all shipments to Huawei after 15 September 2020 [12].

Huawei's fallback was [SMIC](https://aiwiki.ai/wiki/smic), whose 7nm-class N+2 node is produced without extreme ultraviolet lithography because [ASML](https://aiwiki.ai/wiki/asml) EUV tools cannot be exported to China. CSET's analysis of the Ascend 910B found the shift visible in the silicon itself: the 910B runs 20 to 25 active AI cores against the original's 30 to 32, a reduction the authors read as either weak yields or a deliberate die-size cut to squeeze more usable parts from constrained wafer capacity [10]. The Financial Times, citing unnamed sources, put Huawei's overall Ascend programme yield near 40 percent by February 2025, against about 20 percent a year earlier, and still short of the 60 to 70 percent those reports treat as a normal commercial threshold [13][32].

Sanctions leakage complicated the picture further. In October 2024 the analysis firm [TechInsights](https://aiwiki.ai/wiki/techinsights) found a TSMC-fabricated die inside an Ascend 910B, and TSMC subsequently suspended shipments to the Chinese design house Sophgo [14]. Reporting in March 2025 on a Center for Strategic and International Studies assessment put the volume of TSMC-made Ascend 910B logic dies obtained through intermediaries at more than two million [15].

On 13 May 2025 BIS published guidance applying General Prohibition 10 to Chinese advanced-computing integrated circuits, stating that named chips "were likely developed or produced in violation of U.S. export controls" and listing the Huawei Ascend 910B, 910C, and 910D by name as presumptively covered [6]. The practical effect is that using, selling, servicing, or financing those parts anywhere, not only exporting them, can expose a company to US enforcement.

## Generations

| Generation | Public debut | Fabrication | Notes |
| --- | --- | --- | --- |
| Ascend 310 | November 2018 | 12nm | 16 TOPS INT8, 8 TFLOPS FP16, 8 W, 2 Da Vinci cores [1][2] |
| Ascend 910 | August 2019 | TSMC 7nm-plus (EUV) | 256 TFLOPS FP16 as announced, 310 W max, 32 Da Vinci cores, 456 mm2 compute die [1][3] |
| [Ascend 910B](https://aiwiki.ai/wiki/huawei_ascend_910b) | 2022-2023, no public launch event | SMIC 7nm (N+2); most examined dies TSMC 7nm from the Sophgo die bank | 400 FP16 TFLOPS, HBM2e at 1,600 GB/s, 192 MB on-chip memory, 20-25 active cores, per CSET analysis [10] |
| [Ascend 910C](https://aiwiki.ai/wiki/huawei_ascend_910c) | Mass shipments to Chinese customers reported from May 2025 [34] | SMIC 7nm (N+2); most examined dies TSMC 7nm from the Sophgo die bank | Dual-die package, 24 cube and 48 vector cores per die, eight shared on-package memory stacks [16] |
| Ascend 910D | Reported in testing, April 2025 | Not disclosed | Named in BIS GP10 guidance; Huawei has not published specifications [6][18] |
| Ascend 950PR / 950DT | Announced for Q1 and Q4 2026 | Not disclosed | 1 PFLOPS FP8 target, Huawei's own HiBL 1.0 and HiZQ 2.0 memory [19] |

The 910B and 910C have dedicated articles; this page covers the family rather than the individual parts.

## Atlas systems and CloudMatrix 384

Huawei's answer to the per-chip gap with NVIDIA has been to sell larger coherent domains. In March 2025 it launched the Atlas 900 A3 SuperPoD, which packs up to 384 Ascend 910C chips and is rated at up to 300 PFLOPS; by September 2025 Huawei said more than 300 of them had been deployed [19]. Huawei Cloud offers the same 384-chip supernode as CloudMatrix384 [16].

A June 2025 arXiv paper from Huawei, with co-authors from the inference provider SiliconFlow, documents the design in unusual detail for a Chinese accelerator [16]. Each Ascend 910C in the system is a dual-die package whose two compute dies share eight on-package memory stacks; each die carries 24 AI cube cores for matrix work and 48 AI vector cores for element-wise operations, supports FP16, BF16, and INT8, and integrates seven 224 Gbps transceivers onto a scale-up Unified Bus plane plus a separate RDMA interface for scale-out. The supernode spans 16 racks, 12 of compute holding 48 nodes and 384 NPUs in total plus four housing the second-tier Unified Bus switches, alongside 192 Kunpeng CPUs. Bandwidth degradation between nodes is under 3 percent relative to intra-node traffic, which is what allows the rack group to be scheduled as one machine. Serving [DeepSeek-R1](https://aiwiki.ai/wiki/deepseek_r1) with 320-way expert parallelism and INT8 quantization, the authors report prefill throughput of 6,688 tokens per second per NPU and decode throughput of 1,943 tokens per second per NPU within a 50 ms per-output-token budget, falling to 538 tokens per second per NPU under a 15 ms latency constraint [16].

The independent read is that the design buys performance with power. [SemiAnalysis](https://aiwiki.ai/wiki/semianalysis) calculated in April 2025 that CloudMatrix 384 offers about 300 PFLOPS of dense BF16 compute, close to double the [GB200 NVL72](https://aiwiki.ai/wiki/nvidia_gb200_nvl72), with 3.6 times the aggregate memory capacity and 2.1 times the memory bandwidth, while drawing 4.1 times the power and landing 2.5 times worse on power per FLOP [17]. The firm noted that electricity is a weaker constraint in China than in the United States, which changes how that trade looks to a Chinese buyer.

At the World Artificial Intelligence Conference (WAIC) in Shanghai in July 2026, Huawei said the 384-chip supernode had been deployed in more than 750 commercial projects across sectors including internet services, telecommunications, and finance [20].

## CANN, MindSpore, and the software problem

CANN, short for Compute Architecture for Neural Networks, is the layer between AI frameworks and Ascend silicon, and it is the closest analogue to [CUDA](https://aiwiki.ai/wiki/cuda) in Huawei's stack. Huawei's own description splits it into a driver layer, a runtime that executes compiled work, and libraries including domain-specific acceleration libraries and the Huawei collective communication library, with a graph engine compiling and optimizing computation graphs from multiple frameworks [16]. Developers write custom operators in Ascend C, a C-like kernel language; the 2019 Hot Chips deck described the same idea as a tiered stack of compilers and operator libraries running underneath [PyTorch](https://aiwiki.ai/wiki/pytorch), [TensorFlow](https://aiwiki.ai/wiki/tensorflow), and MindSpore [1].

MindSpore is Huawei's own training and inference framework, announced alongside the Ascend strategy in October 2018 and open sourced in March 2020 under the Apache 2.0 license with backends for Ascend, GPUs, and CPUs [21][22]. At the 2019 launch Huawei claimed MindSpore needed about 20 percent fewer lines of core code than leading frameworks for typical NLP models [3].

Software has been the family's most persistent weakness, and Huawei's 2025 response was to give the stack away. At an Ascend computing industry summit in Beijing on 6 August 2025 the company announced a full open-source release of CANN, and later described the Mind series toolkits as open sourced alongside it [23][20]. At HUAWEI CONNECT the following month, Ascend Computing president Zhang Dixuan said all CANN operators would be published on GitCode by late September, with domain libraries, the graph engine, Ascend C, and the MindIE inference engine following in December, and committed 1,500 PFLOPS of compute and 30,000 development boards a year to ecosystem work [24]. By WAIC 2026 Huawei reported the CANN community at 67 projects and more than 3,500 monthly active developers [20]. Whether that closes the gap is unsettled: coverage of the open-source announcement noted that CUDA has been maintained and refined continuously for close to two decades, and that matching its library depth and documentation would likely take CANN years [33].

## Adoption in China

Ascend adoption accelerated once high-end NVIDIA parts became hard to buy. Huawei Cloud and the inference provider SiliconFlow launched hosted [DeepSeek](https://aiwiki.ai/wiki/deepseek) V3 and R1 services on Ascend silicon in February 2025 [25]. iFlytek has said it trains its Spark models entirely on Huawei computing hardware, and in April 2025 described its Spark X1 reasoning model as trained wholly on domestic infrastructure [7]. Huawei's own Pangu Ultra, a 135-billion-parameter dense [large language model](https://aiwiki.ai/wiki/large_language_model), was pre-trained on 13.2 trillion tokens using 8,192 Ascend NPUs [8].

Policy pushed the same direction. In November 2025 Reuters reported that Beijing had issued guidance requiring new state-funded data center projects to use only domestically made AI chips [26]. Bloomberg reported in September 2025 that Huawei planned to roughly double Ascend 910C output to about 600,000 units in 2026, with total Ascend output reaching as many as 1.6 million dies across the line [27]. In March 2026 Reuters reported that [ByteDance](https://aiwiki.ai/wiki/bytedance) and [Alibaba](https://aiwiki.ai/wiki/alibaba) intended to place orders after customer testing of Huawei's newest chip went well [28], and in May 2026 that Huawei expected AI chip revenue to rise at least 60 percent over the year [29].

## Roadmap through 2028

At HUAWEI CONNECT 2025 on 18 September, Eric Xu published an Ascend roadmap running to 2028 [19]. The Ascend 950 series is rated at 1 PFLOPS in FP8, MXFP8, and Huawei's HiF8 format, and 2 PFLOPS in MXFP4. It arrives in two variants: the 950PR in Q1 2026, using Huawei's own HiBL 1.0 memory and aimed at the prefill stage of inference and at recommendation systems, and the 950DT in Q4 2026 with HiZQ 2.0 memory at 144 GB and 4 TB/s, plus 2 TB/s of interconnect bandwidth. The Ascend 960 is slated for Q4 2027 with twice the 950's compute, memory bandwidth, memory capacity, and interconnect ports, and the Ascend 970 for Q4 2028 with double the 960's FP8 and FP4 throughput and interconnect bandwidth again. Developing memory in house is the notable part, since [high-bandwidth memory](https://aiwiki.ai/wiki/high_bandwidth_memory) supply has been one of the family's hardest external dependencies.

The systems roadmap scales further. Huawei described an Atlas 950 SuperPoD of up to 8,192 Ascend 950DT chips at 8 EFLOPS FP8 and 16 EFLOPS FP4 for Q4 2026, and an Atlas 960 SuperPoD of up to 15,488 chips at 30 EFLOPS FP8 for Q4 2027, with SuperCluster configurations of more than 520,000 and more than one million NPUs respectively, all built on a UnifiedBus 2.0 interconnect whose specifications were released at the same event [19]. Huawei showed the Atlas 950 SuperPoD outside China for the first time at MWC Barcelona on 2 March 2026, presented by computing product line president Seaway Zhang [30], and displayed a 1,024-NPU physical unit at WAIC in Shanghai in July 2026, quoting 1 EFLOPS FP8, 2 EFLOPS FP4, a 256 TB global address space, and 3 microsecond round-trip latency [20][31].

## Limitations

The binding constraint remains manufacturing. SMIC's 7nm-class N+2 process runs without EUV lithography, and CSET reads the Ascend 910B's reduced active core count as a sign of either weak yields or a deliberate effort to extract more usable dies from SMIC's limited 7nm capacity [10]. Memory is the second constraint, which is why the published roadmap moves to Huawei's self-developed HiBL and HiZQ stacks rather than purchased HBM [19].

Efficiency is the third. The SemiAnalysis figures for CloudMatrix 384 quantify the trade Huawei is making: competitive aggregate throughput at a substantial penalty in power per unit of work [17]. That is tolerable inside China and awkward anywhere electricity is scarce or expensive.

Finally, the BIS GP10 guidance creates legal exposure that has nothing to do with the silicon. Because the guidance covers use and servicing rather than only export, non-Chinese firms face real risk in touching Ascend hardware at all, which in practice limits the family's market to China and to buyers willing to accept that risk [6]. BIS carved out an exception only for parties acquiring a chip solely for technical analysis such as destructive testing [6].

## See also

- [Huawei Ascend 910B](https://aiwiki.ai/wiki/huawei_ascend_910b)
- [Huawei Ascend 910C](https://aiwiki.ai/wiki/huawei_ascend_910c)
- [Huawei CloudMatrix 384](https://aiwiki.ai/wiki/huawei_cloudmatrix_384)
- [CANN](https://aiwiki.ai/wiki/cann)
- [MindSpore](https://aiwiki.ai/wiki/mindspore)
- [SMIC](https://aiwiki.ai/wiki/smic)

## References

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