# Huawei Ascend 910B

> Source: https://aiwiki.ai/wiki/huawei_ascend_910b
> Updated: 2026-07-14
> Categories: AI Hardware, AI Infrastructure, Chinese AI
> License: CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/)
> From AI Wiki (https://aiwiki.ai), the free encyclopedia of artificial intelligence. Reuse freely with attribution to "AI Wiki (aiwiki.ai)".

| Field | Value |
| --- | --- |
| Type | Data-center AI training and inference accelerator (NPU) |
| Designer | HiSilicon (a [Huawei](/wiki/huawei) subsidiary) |
| Series | Huawei Ascend |
| Architecture | Da Vinci (Da Vinci Max AI cores) |
| Fabrication | 7nm class: SMIC (variously called N+1 or N+2); many examined dies were made by [TSMC](/wiki/tsmc) N7+ |
| Introduced | 2023 (mass shipments); design derived from the 2019 Ascend 910 |
| AI cores | About 25 Da Vinci cores (roughly 20 to 25 active) |
| Compute die | About 665.61 mm-squared (21.32 by 31.22 mm), per TechInsights |
| FP16 / BF16 compute | About 320 to 400 TFLOPS (SemiAnalysis estimates ~376); some reports up to ~600 |
| INT8 | About 640 TOPS |
| Memory | 64 GB HBM2e (910B1 to 910B3); 32 GB (910B4) |
| Memory bandwidth | About 1.2 to 1.6 TB/s |
| Interconnect | HCCS (three ports, 30 GB/s each); 200 Gb RoCE for scale-out |
| Typical system | Atlas 300T card; Atlas 800 (model 9000) server with 8 accelerators |
| Power (TDP) | About 310 to 400 W |
| Successor | [Huawei Ascend 910C](/wiki/huawei_ascend_910c) (packages two 910B dies) |

**The Huawei Ascend 910B** is a data-center [AI accelerator](/wiki/ai_chip) designed by Huawei's HiSilicon unit that became China's most widely deployed domestic alternative to restricted NVIDIA data-center GPUs across roughly 2023 and 2024. Built on Huawei's proprietary Da Vinci architecture and a 7-nanometer-class process, it is the compute die that Huawei's later [Ascend 910C](/wiki/huawei_ascend_910c) pairs two of in a single package, making the 910B the foundational silicon of Huawei's whole current AI-accelerator line.[1][2][5] Huawei has never published a full 910B datasheet, so most of the specific numbers in circulation are analyst estimates, teardown findings, and supply-chain reporting rather than vendor-confirmed specifications, and they should be read that way throughout this article.[2][4][5]

The 910B matters less as a chip that beats NVIDIA than as the part that proved China could field a domestically usable, high-volume training accelerator while cut off from the best Western hardware. It anchored the first wave of large Chinese AI clusters built without NVIDIA A100 and H100 GPUs, was adopted under supply pressure by companies such as Baidu, ByteDance, and iFlytek, and set the template (scale out many chips rather than win per chip) that Huawei carried forward into the 910C and its [CloudMatrix 384](/wiki/huawei_cloudmatrix_384) rack systems.[6][9][10][13]

## Background and place in the Ascend line

Huawei introduced the Ascend brand at its 2018 Connect conference as the training-and-inference tier of a "full-stack, all-scenario" AI portfolio, with all Ascend parts sharing the Da Vinci microarchitecture that HiSilicon presented at Hot Chips in 2019.[1] The line began with the low-power Ascend 310 inference chip in 2018, followed by the flagship Ascend 910 for data-center training, which Huawei launched on August 23, 2019, and marketed at the time as "the world's most powerful AI processor."[1] That original 910 was fabricated by [TSMC](/wiki/tsmc) on its N7+ process (7nm with several extreme-ultraviolet, or EUV, layers), carried 32 Da Vinci Max cores plus 16 Arm-compatible Taishan CPU cores, and was rated at roughly 256 TFLOPS of FP16 compute and 512 TOPS of INT8 within about a 310-watt envelope, with 32 GB of HBM2 memory.[1] A cluster of 2,048 of these first-generation chips trained Huawei's 200-billion-parameter PanGu-Alpha [language model](/wiki/large_language_model) in 2021.[1]

The 910B is a distinct silicon design that shares the Ascend 910 branding but almost none of the original layout. It exists because United States [export controls](/wiki/export_controls) severed HiSilicon's access to TSMC. After the US Commerce Department tightened the Foreign Direct Product Rule in May 2020, TSMC stopped manufacturing new chips for Huawei, forcing HiSilicon to redesign the 910 so it could be built domestically at a less advanced foundry.[4] The result reached mass shipment in 2023 as the Ascend 910B, positioned squarely as the leading Chinese substitute for NVIDIA parts that could no longer be sold into the country. The 910B in turn became the building block for the dual-die 910C reported through 2024 and 2025, which analysts and Reuters describe as two 910B compute dies packaged together to roughly double per-package performance.[5][6]

## Architecture: Da Vinci cores and packaging

The Ascend 910B is built on Da Vinci Max, the high-performance variant of Huawei's Da Vinci architecture. Each Da Vinci AI core is organized as a hierarchy of compute units of different dimensionality: a 3D Cube unit that performs the dense matrix multiply-accumulate operations at the heart of [deep learning](/wiki/deep_learning), a 2D Vector unit for activations, normalization, and element-wise math, and a 1D Scalar unit for control flow and addressing.[1] Teardown analysis by the firm TechInsights, reported in detail by Tom's Hardware, found that the 910B compute die carries about 25 Da Vinci cores, down from 32 in the TSMC-built original, with each core pairing one matrix execution unit to two vector units.[2][3] Independent analysis compiled by Georgetown's Center for Security and Emerging Technology (CSET) put the count of active cores at roughly 20 to 25, running at about 1.5 to 1.8 GHz depending on the SKU, and noted that the 910B roughly doubled on-chip cache to about 192 MB from 32 MB in the first generation.[4]

The single most striking physical fact about the 910B is its size. TechInsights measured the compute chiplet at 21.32 by 31.22 millimeters, about 665.61 square millimeters, far larger than the roughly 456-square-millimeter die of the TSMC-built 910.[2][3] The enlargement is a direct consequence of manufacturing on a less advanced, non-EUV process: to hit its performance target without the density that EUV lithography provides, HiSilicon spread the design across much more silicon. That larger die is central to the yield and cost problems discussed below.

On packaging, the 910B integrates its Da Vinci cores, Arm-compatible CPU cores, and HBM stacks so the accelerator can handle system-level tasks without leaning entirely on a separate host processor, a hallmark of the Ascend 910 family.[3][4] The 910C extends this by placing two 910B-class dies in one package linked by a high-bandwidth interconnect so software sees a single accelerator; that 910C-specific dual-die design is covered on its own page and is not repeated here.[5][6]

## Fabrication: SMIC, TSMC, and the die bank

The manufacturing story of the 910B is the most contested part of its record, and it is more complicated than the common shorthand. The popular description is that the 910B is a fully "homegrown" chip made by China's leading foundry, SMIC, on a 7nm-class process (described in different sources as SMIC's N+1 or N+2 node, using older deep-ultraviolet lithography rather than EUV).[2][4] Under that account, the 910B was the first high-performance Chinese AI training chip fabricated entirely inside China, and the enlarged 665-square-millimeter die reflects the compromises of building 7nm-class logic without EUV.[2]

The more detailed analyst account complicates that narrative. SemiAnalysis reported in 2025 that the great majority of Ascend 910B and 910C dies it examined were actually manufactured on TSMC's 7nm process, not SMIC's, and independent TechInsights teardowns found TSMC-made dies inside Ascend samples.[5] According to multiple reports, Huawei obtained those dies despite the 2020 TSMC cutoff through an intermediary: a Cayman Islands-registered company called Sophgo purchased roughly 500 million dollars of TSMC 7nm wafers, which were routed to Huawei and amounted to about 2.9 million dies usable across both the 910B and the 910C.[5][7][8] US authorities treated the arrangement as a sanctions-evasion scheme; TSMC cut off Sophgo, reported the matter, and faced potential penalties. SemiAnalysis framed this stockpile as a TSMC "die bank" that carried Huawei's Ascend production through 2024 and 2025 and projected it would run down over roughly the following year, after which SMIC would take over volume production.[5]

Both descriptions are partly true depending on the batch and date: some 910B units use SMIC-fabricated compute dies, while many others use TSMC dies drawn from the stockpiled die bank. This is exactly why the "SMIC 7nm chip" label is imprecise, and any single confident statement about who fabricated a given 910B should be attributed to its source and treated as provisional.[2][5] SemiAnalysis's broader assessment was that fabrication was not even the binding constraint going forward; the gating factor was high-bandwidth memory (HBM), where China had stockpiled foreign stacks (Samsung the leading supplier) ahead of tightened controls in late 2024, and the exhaustion of that HBM inventory, more than wafer capacity, would cap how many Ascend accelerators Huawei could build.[5]

## Specifications

Because Huawei publishes no official 910B datasheet, the table below collects the most commonly cited figures and their sources. Numbers vary meaningfully across analysts, teardowns, and secondary compilations, especially for FP16 throughput, and every entry should be read as an attributed estimate.

| Specification | Reported figure | Source basis |
| --- | --- | --- |
| AI cores | About 25 Da Vinci cores (20 to 25 active) | TechInsights teardown, CSET [2][3][4] |
| Compute die area | About 665.61 mm-squared (21.32 by 31.22 mm) | TechInsights [2][3] |
| Clock speed | About 1.5 to 1.8 GHz (SKU-dependent) | CSET [4] |
| FP16 / BF16 compute | About 320 to 400 TFLOPS (SemiAnalysis ~376); up to ~600 in some reports | Tom's Hardware, CSET, SemiAnalysis [2][4][5] |
| INT8 | About 640 TOPS | Tom's Hardware teardown [2] |
| On-chip cache | About 192 MB | CSET [4] |
| Memory | 64 GB HBM2e (910B1 to 910B3); 32 GB (910B4) | CSET [4] |
| Memory bandwidth | About 1.2 to 1.6 TB/s (up to 1,600 GB/s on top SKUs) | CSET, others [4] |
| Fabrication | SMIC 7nm (N+1/N+2), or TSMC N7+ on die-bank units | Tom's Hardware, SemiAnalysis [2][5] |
| Interconnect | HCCS (three ports, 30 GB/s each); 200 Gb RoCE | Huawei Atlas docs [14] |
| Power (TDP) | About 310 to 400 W | CSET, teardown reporting [2][4] |

The spread in the FP16 figure is worth spelling out. A teardown-derived estimate reported by Tom's Hardware put the 910B near 320 TFLOPS of FP16 with about 640 TOPS of INT8; CSET's analysis put the top 910B SKUs near a marketed 400 TFLOPS but cautioned that, on a consistent accounting basis, the real generational gain over the 256-to-320-TFLOPS first-generation 910 was marginal, only on the order of 60 TFLOPS, with part of the headline improvement coming from a change in how the number was counted.[2][4] SemiAnalysis independently modeled the 910B at roughly 376 TFLOPS of FP16, a figure that lines up neatly with its estimate of about 754 TFLOPS for the two-die 910C.[5] Some secondary compilations cite figures as high as about 600 TFLOPS. The safest reading is that a single 910B delivers somewhere in the low hundreds of FP16 TFLOPS, well under a modern NVIDIA data-center GPU, with the exact number unsettled.

## Interconnect and systems: HCCS, Atlas 800 and Atlas 900

A single accelerator is only useful at scale if many can be lashed together, and here the 910B relies on Huawei's own interconnect fabric rather than NVIDIA's NVLink. Each 910B exposes three HCCS (Huawei Cache Coherence System) ports running at about 30 GB/s each, enough to fully connect a group of chips inside a server, plus high-speed Ethernet supporting RDMA over Converged Ethernet (RoCEv2) for communication between chassis.[14] The standard building block is the Atlas 800 training server (model 9000), a 4U system that packs eight Ascend 910B accelerators alongside four Kunpeng 920 Arm server CPUs, with the eight accelerators fully interconnected over HCCS and up to eight 200-gigabit RoCE links for scale-out.[14]

Above the server sits the Atlas 900 cluster tier, which strings many Atlas 800 nodes together. A typical Atlas 900 PoD configuration links eight nodes for 64 accelerators and roughly 4 TB of aggregate memory, using a mix of HCCS, PCIe, and 100-gigabit Ethernet interconnects with a dedicated non-blocking synchronization network, enough to train models in the low hundreds of billions of parameters with appropriate parallelism.[15] This tiered approach (HCCS inside the box, high-speed Ethernet across boxes) is the direct ancestor of the optical, rack-scale [CloudMatrix 384](/wiki/huawei_cloudmatrix_384) system that Huawei later built around the 910C, and it embodies the same strategy: compensate for a weaker individual chip by connecting a great many of them with high bandwidth.[6][15]

## Software stack: CANN, MindSpore, and CUDA friction

Hardware is only half of the 910B story, and software is where Huawei both invests heavily and faces its most durable disadvantage. In place of NVIDIA's CUDA, the Ascend line uses [CANN](/wiki/cann) (Compute Architecture for Neural Networks), Huawei's heterogeneous computing stack that sits between high-level AI frameworks and Ascend silicon, together with the MindSpore deep-learning framework and libraries such as the HCCL collective-communication library for distributed training.[1] CANN is compatible with MindSpore, PyTorch, and TensorFlow, but porting and tuning workloads for it requires real engineering effort, and the surrounding ecosystem of optimized kernels, tools, and community know-how is far smaller than the roughly two decades of accumulated CUDA support.[4]

That software gap, rather than raw silicon, is what analysts most often flag as the hardest thing for Huawei to close quickly, and it shows up directly in 910B deployments. When [DeepSeek](/wiki/deepseek) evaluated Ascend hardware, its engineers noted that squeezing competitive efficiency out of the chips required hand-optimizing kernels, and that DeepSeek's native support for Ascend was meant to ease conversion of CUDA code to the Ascend stack.[11][12] Huawei has moved to narrow the gap by open-sourcing CANN and the Mind-series tools through 2025, aiming to grow a developer base around Ascend the way NVIDIA grew one around CUDA.[1]

## Performance versus NVIDIA

Comparing the 910B to NVIDIA's data-center GPUs is unavoidably imprecise, because Huawei publishes no official throughput and because the answer depends heavily on the workload and the metric. The following figures are attributed estimates and ranges, not settled facts.

On raw FP16 throughput, SemiAnalysis put the 910B at roughly 376 TFLOPS against about 989 TFLOPS for NVIDIA's [H100](/wiki/nvidia_h100) on the same basis (the H100 number includes NVIDIA's sparsity feature), a bit under 40 percent, and CSET similarly framed the 910B as well behind a modern NVIDIA part despite the Ascend branding.[4][5] The most-cited single data point comes from DeepSeek, whose researchers reported in early 2025 that the two-die 910C reaches about 60 percent of an H100's inference performance; since the 910C is two 910B dies, this implies a single 910B lands well below one H100 for inference.[11][12] DeepSeek engineers also stressed that training, not inference, is where Chinese chips struggle most, citing long-run reliability as a critical weakness.[11]

The export-compliant NVIDIA parts that Chinese buyers could legally obtain are the relevant baseline for much of this comparison. The [H800](/wiki/nvidia_h800) was an H100 variant made for China with its chip-to-chip interconnect cut down (NVLink reduced from about 900 to roughly 400 GB/s) but broadly similar raw compute, until it too was banned in October 2023; the [H200](/wiki/nvidia_h200) pairs H100-class compute with 141 GB of faster HBM3e and about 4.8 TB/s of bandwidth, widening the memory gap against the 910B's roughly 64 GB and 1.2-to-1.6 TB/s.[5] Rather than reduce this to a single ratio, the honest summary is that a 910B delivers somewhere between roughly one-third and 60 percent of an H100-class part depending on the workload measured, and less on memory-bound and training tasks than on well-tuned inference. Because a standard training server packs eight accelerators on either side, the per-server throughput gap tracks the per-chip gap, on the order of two to four times fewer effective tokens, which is consistent with DeepSeek's framing that operating under export controls forces Chinese teams to spend two to four times the compute to reach the same result, a structural penalty examined in detail by analysts at Epoch AI.[5][11][16]

A concrete illustration of how far tuning can move the number comes from iFlytek. According to founder Liu Qingfeng, at the end of 2024 the 910B ran reasoning-model training at only about 20 percent of the efficiency of NVIDIA's solution, but iFlytek and Huawei engineers jointly raised that to nearly 80 percent over the following months, showing both the size of the initial gap and how much of it is software and optimization rather than fixed silicon.[13]

## Deployment and real-world use

The 910B's importance is best measured in who bought it under pressure. In August 2023, Baidu placed an order for 1,600 Ascend 910B chips worth roughly 450 million yuan (about 61.8 million dollars) as an alternative to NVIDIA parts, and by October 2023 Huawei had reportedly delivered more than 60 percent of that order, around 1,000 chips, according to Reuters reporting summarized by TechNode.[9] The order was explicitly framed as preparation for a future in which Baidu might no longer be able to buy NVIDIA A100-class GPUs at all.[9]

Demand quickly outran supply, a pattern that defined the 910B era. ByteDance was reported to have ordered more than 100,000 Ascend 910B chips, but had received fewer than 30,000 (under 30 percent) as of mid-2024, with the shortfall tied to a 910B yield reported at around 50 percent.[10] SemiAnalysis estimated that Huawei shipped roughly 507,000 Ascend units in 2024, the majority of them 910Bs, and that the binding limit on going higher was HBM rather than the chips themselves.[5] Other named 910B users include Tencent, China Mobile, and Chinese-government-affiliated data centers, and by 2025 IDC data reported via Reuters showed Huawei leading domestic AI-accelerator shipments in China with roughly 812,000 Ascend cards, about half of all domestic shipments.[4][27]

The highest-profile validation came from iFlytek, which trained its Xinghuo (Spark) X1 reasoning model entirely on Ascend 910B hardware and, in early 2025, said the model matched OpenAI's o1 and DeepSeek's R1 in overall performance, presenting it as evidence that a fully domestic hardware-and-software stack could train a frontier-class reasoning model.[13] DeepSeek's own experience was more mixed: the Financial Times reported in August 2025 that DeepSeek delayed its R2 model after failing to complete a training run on Ascend hardware even with a Huawei engineering team on site, and reverted to NVIDIA chips for training while continuing to use Ascend for inference, underscoring the persistent training-reliability gap.[25]

## Supply constraints, geopolitics, and China's compute economics

The 910B sits at the center of the debate over whether US export controls have slowed China's AI progress or mainly redirected it toward domestic suppliers. On the supply side, the chip has faced three overlapping constraints: the low yield of a very large die on a non-EUV 7nm-class process (reported around 50 percent for the 910B), the finite TSMC die bank that supplied many of its compute dies, and, above all, access to HBM, which SemiAnalysis identified as the true bottleneck on Ascend volume once wafer capacity was no longer limiting.[5][10]

On the policy side, the 910B has been swept up in the tightening of controls. The US barred NVIDIA's A100 and H100 from China in October 2022, banned the China-market H800 and A800 in October 2023, and suspended NVIDIA's further-cut-down H20 in April 2025.[4][5] In May 2025 the US Bureau of Industry and Security issued guidance stating there was a "high probability" that Huawei's Ascend 910B, 910C, and 910D were developed or produced in violation of export controls, warning that transactions involving the chips risked enforcement action, before the agency revised the notice to remove language saying that using the chips "anywhere in the world" would violate the rules.[17][18] An October 2025 report from the Information Technology and Innovation Foundation argued that the controls had paradoxically strengthened Huawei by insulating it from foreign competition inside China while forcing it to build a self-sufficient stack.[26]

Huawei's own leadership frames the position candidly: founder Ren Zhengfei said in a June 2025 interview that the company remains "one generation behind" in single-chip performance and closes the gap through clustering and mathematics rather than leading-edge fabrication, a description that fits the 910B precisely.[28] The economic logic that keeps the 910B viable, despite conceding per-chip performance, is scale plus cheap power. Because each accelerator is far less capable and far less efficient than NVIDIA silicon (SemiAnalysis estimated Huawei's rack-scale systems draw roughly 2.5 times more power per unit of compute), China's approach is to deploy many more chips and absorb the higher electricity draw, which is more tolerable where power is abundant and cheap.[6] That is the rationale behind China's "Eastern Data, Western Computing" (dong shu xi suan) program, launched in February 2022, which routes compute to western provinces such as Guizhou, Gansu, and Inner Mongolia that offer some of the world's lowest industrial power rates and abundant renewable energy.[23][24] In June 2026, Bloomberg reported that China's National Development and Reform Commission was drafting a plan to spend about 295 billion dollars (on the order of 2 trillion yuan) over five years on a national network of AI data centers, relying on domestic suppliers including Huawei for at least 80 percent of AI chips and effectively squeezing out NVIDIA.[19][20]

Financial analysts have tried to quantify the resulting trade-off. Goldman Sachs, in mid-2026 research, projected Chinese AI-infrastructure capital spending of more than 70 billion dollars in 2026 and forecast domestic daily token consumption rising steeply toward the end of the decade, while flagging that China's stack is optimized to do more with less rather than to close the absolute compute gap.[21][22] DeepSeek's own framing of that penalty (two to four times the compute for the same result) captures the per-unit disadvantage that the 910B embodies.[11][16] A widely shared July 2026 social-media summary attributed to a Goldman report a sharper claim, that the 910B and 910C yield only about one-sixth to one-third of an H800's daily token output; that specific ratio could not be verified against the underlying Goldman report or reputable coverage and is therefore omitted here, with the attributable, several-fold per-chip and per-server gap presented above in its place.[5][11]

## Plain-language summary

In simple terms, the Ascend 910B is China's home-team answer to the powerful NVIDIA chips it was blocked from buying. Think of NVIDIA's chips as a small number of very fast race cars and the 910B as a slower car that China can build itself: any one 910B is clearly weaker, delivering maybe a third to 60 percent of a top NVIDIA chip depending on the job, and it is harder to program because it uses Huawei's own software instead of the industry-standard NVIDIA tools. China's workaround is to run a much larger fleet of these slower cars and pay the higher electricity bill, siting the data centers in its western regions where power is cheap. That is why the 910B is a big deal even though it loses the head-to-head race: it let Chinese companies keep training and running large AI systems on their own hardware while shut out of the best imports.

## See also

- [Huawei Ascend 910C](/wiki/huawei_ascend_910c)
- [Huawei AI](/wiki/huawei_ai)
- [Huawei CloudMatrix 384](/wiki/huawei_cloudmatrix_384)
- [CANN](/wiki/cann)
- [AI chip](/wiki/ai_chip)
- [NVIDIA H100](/wiki/nvidia_h100)
- [NVIDIA H800](/wiki/nvidia_h800)
- [Export controls](/wiki/export_controls)
- [China AI](/wiki/china_ai)
- [DeepSeek](/wiki/deepseek)

## References

1. Huawei. "Huawei Launches Ascend 910, the World's Most Powerful AI Processor, and MindSpore, an All-scenario AI Computing Framework." Press release, August 23, 2019 (reproduced by the Edge AI and Vision Alliance). https://www.edge-ai-vision.com/2019/08/huawei-launches-ascend-910-the-worlds-most-powerful-ai-processor-and-mindspore-an-all-scenario-ai-computing-framework/
2. Tom's Hardware. "Huawei's homegrown AI chip examined: Chinese fab SMIC-produced Ascend 910B is massively different from the TSMC-produced Ascend 910." 2024. https://www.tomshardware.com/tech-industry/artificial-intelligence/huaweis-homegrown-ai-chip-examined-chinese-fab-smic-produced-ascend-910b-is-massively-different-from-the-tsmc-produced-ascend-910
3. TechInsights. "Huawei Ascend 910B AI Trainer, Die Analysis." 2024. https://library.techinsights.com/hg-asset/23d95da6-7c04-4e9e-a82b-a6702a8757df
4. Center for Security and Emerging Technology (CSET), Georgetown University. "Pushing the Limits: Huawei's AI Chip Tests U.S. Export Controls." https://cset.georgetown.edu/publication/pushing-the-limits-huaweis-ai-chip-tests-u-s-export-controls/
5. SemiAnalysis. "Huawei Ascend Production Ramp: Die Banks, TSMC Continued Production, HBM is The Bottleneck." September 2025. https://newsletter.semianalysis.com/p/huawei-ascend-production-ramp
6. SemiAnalysis. "Huawei AI CloudMatrix 384: China's Answer to Nvidia GB200 NVL72." April 2025. https://newsletter.semianalysis.com/p/huawei-ai-cloudmatrix-384-chinas-answer-to-nvidia-gb200-nvl72
7. Tom's Hardware. "Huawei reportedly acquired two million Ascend 910 AI chips from TSMC last year through shell companies." 2025. https://www.tomshardware.com/tech-industry/artificial-intelligence/huawei-reportedly-acquired-two-million-ascend-910-ai-chips-from-tsmc-last-year-through-shell-companies
8. TechPowerUp. "Huawei Obtained Two Million Ascend 910B Dies from TSMC via Shell Companies to Circumvent US Sanctions." 2025. https://www.techpowerup.com/333877/huawei-obtained-two-million-ascend-910b-dies-from-tsmc-via-shell-companies
9. TechNode (citing Reuters). "Baidu orders AI chips from Huawei as alternative to Nvidia: report." November 8, 2023. https://technode.com/2023/11/08/baidu-orders-ai-chips-from-huawei-as-alternative-to-nvidia-report/
10. Huawei Central (citing Reuters). "ByteDance ordered 100,000 Huawei Ascend 910B chips to replace Nvidia." 2024. https://www.huaweicentral.com/bytedance-ordered-100000-huawei-ascend-910b-chips-to-replace-nvidia/
11. TrendForce. "DeepSeek Reportedly Reveals Huawei's Ascend 910C Reaches 60% of NVIDIA H100's Inference Power." February 5, 2025. https://www.trendforce.com/news/2025/02/05/news-deepseek-reportedly-reveals-huaweis-ascend-910c-reaches-60-of-nvidia-h100s-inference-power/
12. Tom's Hardware. "DeepSeek research suggests Huawei's Ascend 910C delivers 60% of Nvidia H100 inference performance." 2025. https://www.tomshardware.com/tech-industry/artificial-intelligence/deepseek-research-suggests-huaweis-ascend-910c-delivers-60-percent-nvidia-h100-inference-performance
13. South China Morning Post. "No need for Nvidia: iFlytek touts reasoning model trained entirely with Huawei's AI chips." April 23, 2025. https://www.scmp.com/tech/big-tech/article/3307493/no-need-nvidia-iflytek-touts-reasoning-model-trained-entirely-huaweis-ai-chips
14. Huawei. "Atlas 800 Training Server (Model 9000) User Guide, Technical Specifications." https://support.huawei.com/enterprise/en/doc/EDOC1100141955
15. CIO. "Interpretation on Supreme Computing of Huawei Atlas 900 AI Cluster." https://www.cio.com/article/217641/interpretation-on-supreme-computing-of-huawei-atlas-900-ai-cluster.html
16. Epoch AI. "Why China isn't about to leap ahead of the West on compute." https://epoch.ai/gradient-updates/why-china-isnt-about-to-leap-ahead-of-the-west-on-compute
17. U.S. Bureau of Industry and Security. "Guidance on Application of General Prohibition 10 (GP10) to People's Republic of China (PRC) Advanced-Computing Integrated Circuits." May 13, 2025. https://www.bis.gov/media/documents/general-prohibition-10-guidance-may-13-2025.pdf
18. Communications Daily. "BIS Eliminates Language Saying Use of Huawei Ascend Chips 'Anywhere' Violates Export Controls." May 20, 2025. https://communicationsdaily.com/article/2025/05/20/bis-eliminates-language-saying-use-of-huawei-ascend-chips-anywhere-violates-export-controls-2505190030
19. Bloomberg (via The Spokesman-Review). "China preps $295 billion plan to fund nationwide AI buildout." June 2026. https://www.spokesman.com/stories/2026/jun/11/china-preps-295-billion-plan-to-fund-nationwide-ai/
20. Tom's Hardware. "China drafts $295 billion plan to build a national AI data center grid running on 80% domestic chips." June 2026. https://www.tomshardware.com/tech-industry/china-drafts-295-billion-plan-to-build-a-national-ai-data-center-grid-running-on-80-percent-domestic-chips
21. CNBC. "Goldman Sachs picks its favorite Chinese AI models." July 12, 2026. https://www.cnbc.com/2026/07/12/goldman-sachs-picks-its-favorite-chinese-ai-models.html
22. Goldman Sachs. "China's AI providers expected to invest $70 billion in data centers amid overseas expansion." 2026. https://www.goldmansachs.com/insights/articles/chinas-ai-providers-expected-to-invest-70-billion-dollars-in-data-centers-amid-overseas-expansion
23. Al Jazeera. "China's secret weapon in AI race with US? Lots of cheap energy." May 28, 2026. https://www.aljazeera.com/economy/2026/5/28/chinas-secret-weapon-in-ai-race-with-us-lots-of-cheap-energy
24. Jamestown Foundation. "Energy and AI Coordination in the 'Eastern Data Western Computing' Plan." https://jamestown.org/energy-and-ai-coordination-in-the-eastern-data-western-computing-plan/
25. TrendForce (citing the Financial Times). "DeepSeek R2 Model Launch Reportedly Delayed Amid Huawei Ascend Chip Hurdles." August 14, 2025. https://www.trendforce.com/news/2025/08/14/news-deepseek-r2-model-launch-reportedly-delayed-amid-huawei-ascend-chip-hurdles/
26. Information Technology and Innovation Foundation (ITIF). "Backfire: Export Controls Helped Huawei and Hurt U.S. Firms." October 27, 2025. https://itif.org/publications/2025/10/27/backfire-export-controls-helped-huawei-and-hurt-us-firms/
27. WinBuzzer (citing IDC data reported by Reuters). "Chinese Chipmakers Now Hold 41% of China's AI Chip Market." April 3, 2026. https://winbuzzer.com/2026/04/03/chinese-chipmakers-now-hold-41-of-chinas-ai-chip-market-xcxwbn/
28. People's Daily Online. "Huawei founder remains optimistic despite US curbs." June 11, 2025. http://en.people.cn/n3/2025/0611/c90000-20325959.html