# Intel Loihi

> Source: https://aiwiki.ai/wiki/intel_loihi
> Updated: 2026-06-07
> Categories: AI Hardware, Neural Networks
> From AI Wiki (https://aiwiki.ai), a free encyclopedia of artificial intelligence. Quote with attribution.

# Intel Loihi

**Intel Loihi** is a family of research neuromorphic processors developed by Intel Labs to implement spiking neural networks (SNNs) in silicon, with the stated goals of energy-efficient inference, online learning, and real-time event-driven sensor processing.[^1][^2] The first-generation chip (Loihi 1) was announced on September 25, 2017, and packs 128 neuromorphic cores plus three embedded x86 management cores on a 60 mm² die in Intel's 14 nm process, supporting approximately 131,072 leaky-integrate-and-fire neurons and 130 million synapses with programmable on-chip learning.[^1][^3][^4] Loihi 2 followed on September 30, 2021, fabricated on a pre-production version of the Intel 4 process and offering up to one million neurons per chip, fully programmable neuron models, graded spikes, and three-factor learning rules.[^2][^5] In April 2024 Intel unveiled Hala Point, the largest neuromorphic system built to date, which combines 1,152 Loihi 2 chips at Sandia National Laboratories to reach 1.15 billion neurons and 128 billion synapses while drawing at most 2,600 W.[^6][^7] Loihi remains a research platform, distributed exclusively through the Intel Neuromorphic Research Community (INRC) and programmed with Intel's open-source Lava software framework; Intel has not announced a commercial product based on the architecture.[^2][^8]

| Attribute | Loihi 1 | Loihi 2 | Hala Point |
| --- | --- | --- | --- |
| Announcement | 25 Sep 2017[^1] | 30 Sep 2021[^2] | 17 Apr 2024[^6] |
| Process | Intel 14 nm[^3] | Pre-production Intel 4 (EUV)[^2][^5] | Intel 4 (via 1,152 Loihi 2)[^6] |
| Die size | 60 mm²[^3] | Approximately half of Loihi 1[^9] | 12U chassis[^7] |
| Neuromorphic cores | 128[^3] | 128[^9] | 140,544[^7] |
| Embedded x86 cores | 3 (Lakemont)[^3] | 6 (Lakemont)[^9] | 2,304[^7] |
| Neurons per chip | Approximately 131,072[^4] | Up to 1,000,000[^2][^5] | 1.15 billion total[^6] |
| Synapses per chip | Approximately 130 million[^1] | Up to 120 million[^9] | 128 billion total[^6] |
| Transistors | 2.07 billion[^3] | Not officially disclosed | N/A |
| On-chip SRAM | 33 MB[^3] | 192 KiB per core[^9] | N/A |
| Spike payload | Binary[^4] | Graded (integer payload)[^9][^5] | Same as Loihi 2[^7] |
| Neuron model | Fixed LIF with extensions[^3] | Microcode-programmable[^9][^5] | Same as Loihi 2[^7] |
| Peak power | Around 1 W per chip[^9] | Approximately 1 W per chip[^9] | 2,600 W max[^6] |
| Programming framework | Intel NxSDK, then Lava[^2] | Lava[^2][^8] | Lava[^6][^8] |
| Status | Research only[^10] | Research only[^10] | Research only at Sandia[^6] |

## Background

The motivation for Loihi grew out of decades of research into brain-inspired computing, the recognition that conventional deep learning accelerators face severe energy bottlenecks for always-on inference and online adaptation, and the observation that biological neural circuits compute with spikes rather than dense floating-point matrix multiplies.[^3] Mike Davies, director of Intel's Neuromorphic Computing Lab since 2014 and previously the director of silicon engineering at asynchronous design pioneer Fulcrum Microsystems (acquired by Intel in 2011), led the project.[^11] Intel's stated motivation, captured in its September 2017 editorial introducing the chip, was that "the demand for collection, analysis and decision-making from highly dynamic and unstructured natural data is outpacing both classic CPU and GPU architectures," and that a fundamentally new computing primitive would be required for autonomous machines, energy-constrained edge devices, and continuous learning systems.[^1]

Loihi was not Intel's first foray into brain-inspired silicon: it followed earlier prototypes inside Intel Labs and built on the broader neuromorphic engineering tradition started by Carver Mead at Caltech in the late 1980s and extended by efforts such as IBM's TrueNorth (announced 2014), the SpiNNaker manycore system at the University of Manchester led by Steve Furber, and the BrainScaleS analog neuromorphic effort within the European Human Brain Project. Loihi distinguished itself from these contemporaries by combining a fully digital, asynchronous many-core fabric with rich programmable on-chip learning rules at every core, an emphasis that the original IEEE Micro paper by Davies and colleagues highlighted as enabling self-modifying, event-driven computation in a single die.[^3]

Intel formally presented Loihi 1 to the academic community at the Neuro Inspired Computational Elements (NICE) workshop in March 2018 and published a detailed description in IEEE Micro shortly thereafter.[^3] Distribution to outside researchers began in the first half of 2018 through what would become the Intel Neuromorphic Research Community (INRC), a partner program announced in late 2018 that grew into a global ecosystem of academic, government, and industrial collaborators.[^12]

## History and timeline

The Loihi program has gone through several public milestones since its 2017 unveiling, each adding scale, new applications, or a new form factor for researchers in the INRC.

- **September 25, 2017.** Intel announces the original Loihi research test chip in an editorial that describes a self-learning neuromorphic chip with 128 cores, around 130,000 neurons, and 130 million synapses on Intel's 14 nm process.[^1] Intel commits to sharing chips with universities and research institutions in the first half of 2018.[^1]
- **January 2018.** The IEEE Micro article "Loihi: A Neuromorphic Manycore Processor with On-Chip Learning" by Davies and colleagues appears in volume 38, issue 1, providing the architectural reference for Loihi 1.[^3]
- **December 2018.** Intel publicly names the first members of the INRC, including academic and industrial partners drawn from universities, government labs, and large corporations, with Loihi as the architectural focus of the community.[^12]
- **July 2019.** Intel launches Pohoiki Beach, a single-chassis system that integrates 64 Loihi chips on stacks of Nahuku boards to provide approximately 8 million neurons for INRC researchers and reports promising results on sparse coding, [simultaneous localization and mapping (SLAM)](/wiki/slam), path planning, and other workloads.[^13]
- **March 2020.** Intel scales the architecture to 100 million neurons with Pohoiki Springs, a rack-mounted system of 768 Loihi chips on 24 Nahuku boards inside a five-server-sized chassis, drawing under 500 W; Intel positions Pohoiki Springs as a cloud-accessible benchmark platform for the INRC.[^14] In the same month, Intel and Cornell publish work in Nature Machine Intelligence demonstrating one-shot learning of ten hazardous chemical odors on Loihi using a circuit inspired by the mammalian olfactory bulb.[^15]
- **September 30, 2021.** Intel announces Loihi 2 and the open-source Lava framework at the Intel Innovation event, describing Loihi 2 as the first Intel product fabricated with the pre-production Intel 4 (7 nm-class) EUV process and supporting graded spikes, microcode-programmable neuron models, and three-factor learning rules at up to one million neurons per chip.[^2][^5]
- **September 2022.** Intel Labs introduces Kapoho Point, a small eight-chip Loihi 2 development board described as roughly three inches square with four chips on each side, intended for compact robotics and embedded experimentation; the single-chip Oheo Gulch system is the smaller companion.[^16]
- **April 17, 2024.** Intel reveals Hala Point at Sandia National Laboratories, packing 1,152 Loihi 2 chips into a 6U chassis to reach 1.15 billion neurons and roughly 128 billion synapses; Sandia took delivery in early 2024 and uses the system to study brain-scale [neural network](/wiki/neural_network) models and energy-efficient AI workloads on NNSA's Advanced Simulation and Computing program.[^6][^7]
- **2024 to 2025.** The Lava framework continues to be developed in the open at lava-nc on GitHub under a permissive BSD 3 license for the core and LGPL-2.1 for some hardware mapping components, with recent academic work on Loihi 2 (for example, continual learning and sensor fusion case studies) released in late 2024 and 2025.[^8][^17]

Loihi has never been productized for commercial sale. Loihi 1 and 2 systems remain available exclusively to INRC members, either through Intel's neuromorphic research cloud or as physical systems on a loan basis; Intel has emphasized that the architecture is intended to advance the neuromorphic research field rather than to ship as a stand-alone product line.[^10]

## Loihi 1 microarchitecture

Loihi 1 is a fully digital, asynchronous many-core processor designed to compute with spiking neural networks rather than dense tensors. The 60 mm² die, fabricated in Intel's 14 nm FinFET process, contains 2.07 billion transistors organized into 128 neuromorphic cores, three embedded Lakemont x86 management cores, and around 33 MB of on-chip SRAM for synaptic state, while operating across a supply voltage range from 0.50 V up to 1.25 V.[^3]

Each neuromorphic core implements a population of leaky-integrate-and-fire neurons using a discrete-time model. The 128 cores together support roughly 131,072 neurons and 130 million synapses, with up to 16 MB of synaptic memory across the chip in its densest 1-bit synapse format, providing 2.1 million unique synaptic variables per square millimeter, which the original IEEE Micro paper notes is more than three times the density of IBM's TrueNorth at the time.[^3]

A core comprises three main datapath units arranged around the synaptic memory: the SYNAPSE unit fetches synaptic weights and processes incoming spikes from the network, the DENDRITE unit updates the per-neuron state variables (typically a current variable u and a voltage variable v) according to leaky-integrate-and-fire dynamics with optional dendritic compartments and synaptic delays, and the AXON unit generates outgoing spike messages for the fanout cores of each firing neuron.[^3][^18] All updates and message exchanges occur asynchronously: there is no global clock, and time advances on a barrier synchronization at the end of each algorithmic time step.[^3]

Spike messages travel across an asynchronous manycore mesh network-on-chip that carries 32-bit packets containing destination addressing and, optionally, source addressing or payload information; the same fabric also carries x86 management and configuration messages from the three Lakemont cores, which orchestrate the SNN execution but do not participate in spike processing themselves.[^3][^4]

Each core embeds a programmable learning engine that evolves synaptic state variables according to microcode learning rules. Supported rules include pairwise spike-timing-dependent plasticity (STDP), triplet STDP, and various forms of reward-modulated and reinforcement learning, allowing Loihi to perform on-chip adaptation rather than relying on offline gradient-based training, in keeping with the design objective of "fully programmable" plasticity at the synapse.[^3] Intel's pre-silicon analysis of Loihi 1, reported in the IEEE Micro paper, found that mapping the [LASSO](/wiki/lasso_regression) sparse coding problem to a spiking locally competitive algorithm could yield an energy-delay product more than three orders of magnitude superior to a conventional CPU solver on the same problem.[^3]

Externally, Loihi 1 was packaged in several research form factors. Kapoho Bay is a self-contained USB form factor that integrates two Loihi chips with an integrated heatsink and a USB host interface, used by INRC partners for sensor-attached experimentation.[^4] Nahuku boards aggregate larger numbers of Loihi chips for rack-scale systems such as Pohoiki Beach (64 chips, around 8 million neurons) and Pohoiki Springs (768 chips, around 100 million neurons).[^13][^14]

## Loihi 2 microarchitecture

Loihi 2, announced on September 30, 2021, retains the high-level structure of Loihi 1, namely 128 asynchronous neuromorphic cores plus embedded x86 management cores connected by a network-on-chip, but increases nearly every internal capacity and adds substantial programmability.[^2][^9] The die was fabricated with a pre-production version of the Intel 4 process and used EUV lithography to simplify layout design rules, making Loihi 2 the first Intel design to tape out on that node and substantially reducing the silicon area required per neuron and synapse.[^2][^5]

Compared with Loihi 1, the second-generation chip integrates approximately eight times more neurons per core, raising the per-chip neuron count from around 131,072 to up to one million, while the synapse count is held to roughly 120 million per chip (slightly lower than Loihi 1) but with up to 80 times better synaptic utilization in many workloads.[^9] The neuromorphic cores themselves shrunk to roughly half the size at comparable synaptic memory, with 192 KiB of memory per core, allowing the chip overall to occupy roughly half of Loihi 1's die area.[^9] The number of embedded Lakemont x86 cores per chip increased from three to six to better support the higher spike-message bandwidth.[^9] Typical chip power remains around 100 mW in many workloads and up to 1 W at full load, similar to Loihi 1 despite the much greater capacity.[^9]

Three architectural changes in Loihi 2 are particularly important for the workloads INRC researchers have targeted:

- **Programmable neuron models.** Each neuromorphic core in Loihi 2 supports custom neuron models written in a microcoded assembly that exposes arithmetic, comparison, and program control flow operations. This allows researchers to deploy variants such as adaptive LIF, resonate-and-fire, Izhikevich-style models, and other dynamical primitives without redesigning silicon, in contrast to Loihi 1's fixed leaky-integrate-and-fire kernel with parameterized extensions.[^9][^5]
- **Graded spikes.** Loihi 2 spikes carry an integer payload that can encode magnitude information alongside event timing, with some descriptions citing up to 32-bit values per spike, instead of the binary spikes of Loihi 1. Intel and several follow-on academic studies argue that graded spikes let networks solve the same problems with fewer events and fewer neurons, since a single spike can carry a numeric quantity rather than only an event indicator.[^5][^9]
- **Three-factor learning rules.** The learning engine in each core gains support for three-factor learning rules that combine pre-synaptic activity, post-synaptic activity, and a third, often neuromodulatory or reward-like, signal. This allows Loihi 2 to implement biologically inspired plasticity rules that have been proposed as substrates for approximating backpropagation, reinforcement learning, and continual learning entirely on-chip.[^5][^9]

Reported speedups from the architectural redesign include up to 10 times faster spike processing, roughly two times faster neuron state updates, and up to five times faster synaptic operations relative to Loihi 1, with networks running thousands of times faster than the corresponding biological systems in some configurations.[^5][^9] Intel has further reported that Loihi 2 can be more than 100 times more energy-efficient than a [GPU](/wiki/gpu) and roughly 30 times more efficient than a CPU on certain workloads it has profiled.[^19]

Externally, Loihi 2 is packaged in several research systems. Oheo Gulch is a single-chip development platform with a host FPGA; Kapoho Point is a roughly three-inch-square eight-chip board with four chips on each side aimed at edge robotics and compact experimentation; and Hala Point packages 1,152 Loihi 2 chips into a single 12U data-center chassis.[^16][^7]

## Hala Point: the largest neuromorphic system

Hala Point is Intel's flagship Loihi 2 system, announced on April 17, 2024 and operated by [DARPA](/wiki/darpa)-adjacent and NNSA researchers at Sandia National Laboratories. Sandia took delivery of the system in early 2024 (with a photo caption indicating February 1, 2024) and presented it as the largest neuromorphic computing system in the world, packing 1.15 billion artificial neurons into a 6U enclosure roughly the size of a microwave oven.[^6][^7]

Each Hala Point compute complex combines eight Loihi 2 chips; six complexes make up a single 48-chip card; and twelve such cards are aggregated into a 576-chip 6U enclosure, with the full 12U system housing two 576-chip enclosures for a total of 1,152 Loihi 2 chips.[^7] In aggregate the system exposes 140,544 neuromorphic cores, 2,304 embedded x86 host cores, 1.15 billion neurons, and approximately 128 billion synapses (with some Sandia documentation reporting closer to 138.2 billion synapses) backed by a 16 PB/s aggregate memory bandwidth.[^6][^7]

Hala Point is rated at 380 trillion 8-bit synaptic operations per second and 240 trillion neuron operations per second, and on conventional deep neural networks running in 8-bit precision the chassis delivers up to 20 petaops with an efficiency exceeding 15 TOPS/W, all within a maximum power draw of 2,600 W.[^6] When running bio-inspired spiking neural network models at its full 1.15 billion neuron capacity, the system can simulate the networks at roughly 20 times faster than the biological time scale of a comparable nervous system, and at lower neuron capacity it has been reported to reach up to 200 times biological speed on certain benchmarks.[^6]

Sandia's neuromorphic group, led by Brad Aimone and including Craig Vineyard, uses Hala Point to study workloads relevant to the National Nuclear Security Administration's Advanced Simulation and Computing program, with reported research interests spanning physics simulations, climate models, device design, and the development of large-scale neuromorphic primitives. Sandia researchers note that human brains contain on the order of 80 billion neurons and small mammals tens of millions, framing Hala Point's 1.15 billion neurons as roughly comparable to the neuron count of an owl brain or about one percent of a human brain.[^7][^6] Sandia has previously developed a conversion tool called Whetstone that adapts conventional convolutional neural networks into spiking forms suitable for Loihi-class hardware, and similar tooling is being applied on Hala Point.[^20]

Intel describes Hala Point as a successor to Pohoiki Springs (announced in March 2020 with 768 Loihi 1 chips and around 100 million neurons under 500 W) and notes that Hala Point delivers roughly an order of magnitude more compute density and ten times more neuron capacity within a similar power envelope, leveraging Loihi 2's process and architectural improvements.[^6][^14]

## Lava software framework

Lava is Intel's open-source software framework for neuromorphic computing, introduced alongside Loihi 2 in September 2021 and intended to provide a common programming substrate for the neuromorphic research community.[^2][^8] Intel licenses the core of Lava under the permissive BSD 3-Clause license to encourage external contributions, while certain lower-level hardware-mapping components are released under the LGPL-2.1 license; the Loihi extension itself is provided to INRC members only.[^8]

Lava is platform-agnostic and exposes a process-based programming model: applications are described as collections of communicating processes, which can run on conventional CPUs and GPUs during development and then be deployed onto heterogeneous targets that include Loihi 2 hardware once an INRC user installs the proprietary extension.[^2][^8] The framework includes high-level libraries for several application domains, notably lava-dl for spiking deep learning (including SLAYER-style backpropagation training of SNNs) and lava-optimization for constrained optimization workloads such as constraint satisfaction and integer linear programs mapped to neuromorphic primitives.[^8] Intel has positioned Lava as an answer to one of the field's most-cited weaknesses, captured in Mike Davies's observation that "software continues to hold back the field" because, unlike the deep learning ecosystem, neuromorphic computing has historically lacked a unifying programming framework comparable to PyTorch or TensorFlow.[^5]

Independent and academic research on Loihi 2 in 2024 and 2025 has consistently used Lava (for example, recent arXiv preprints on real-time continual learning on Loihi 2 reference Lava 0.11.0.dev0), indicating that the framework is the de facto interface to the platform within the INRC.[^17] The Lava repository at github.com/lava-nc/lava is composed of roughly two-thirds Jupyter notebooks and one-third Python code, reflecting its emphasis on research notebooks and tutorial-style exposition.[^8]

## Intel Neuromorphic Research Community (INRC)

The Intel Neuromorphic Research Community is a global research consortium organized by Intel Labs around the Loihi architecture. Intel publicly named the first cohort of academic, government, and corporate INRC participants on December 6, 2018, with the stated goal of overcoming adoption challenges for neuromorphic architectures and building shared tools, algorithms, and benchmarks.[^12] Membership is by application, and members receive access to Loihi hardware (in cloud-hosted form or, in some cases, as physical systems on loan), to Intel's neuromorphic software stack, and to private collaboration channels with Intel Labs researchers.[^10]

Over time the INRC has expanded from a small research group into an ecosystem of more than 200 organizations that includes leading universities, U.S. national laboratories, neuromorphic startups, and Fortune Global 500 industrial members.[^6] Publicly announced members include Accenture, Airbus, GE, Hitachi, Ford, Mercedes-Benz, Lenovo, Logitech, Prophesee, Georgia Tech, Southwest Research Institute, Teledyne FLIR, and Sandia National Laboratories, among many academic groups.[^12] The community focuses on algorithm and application research using Loihi as a common reference platform, with funded calls (the INRC RFP series) that direct external research toward specific topics such as constrained optimization, continual learning, robotic control, and sensor processing.

## Applications and demonstrations

Researchers inside Intel and across the INRC have published a steady stream of Loihi-based application demonstrations, generally aimed at three goals: showing energy efficiency relative to CPUs and [GPUs](/wiki/gpu) on event-driven workloads, demonstrating low-latency online adaptation, and exploring algorithmic primitives that exploit the timing and sparsity of spikes rather than the dense matrix multiplies of standard deep learning.

- **Neuromorphic olfaction.** In a March 2020 paper in Nature Machine Intelligence, Nabil Imam (Intel) and Thomas Cleland (Cornell University) implemented a neural circuit inspired by the mammalian olfactory bulb on Loihi and trained it to recognize ten hazardous chemicals from the responses of 72 chemical sensors. The system learned each odor from a single sample (one-shot learning) and reportedly matched a deep learning baseline that required around 3,000 times more training samples per class to reach comparable accuracy.[^15]
- **Sparse coding and LASSO.** The original Loihi paper showed that mapping the LASSO sparse coding problem to a spiking locally competitive algorithm running on Loihi could yield an energy-delay product more than three orders of magnitude better than a conventional CPU solver, with pre-silicon benchmarks projecting more than 5,000 times improvement on a large convolutional sparse coding problem.[^3]
- **Simultaneous localization and mapping (SLAM).** Intel and partners have demonstrated [SLAM](/wiki/slam) implementations on Loihi 1 systems, including a Pohoiki Beach configuration that ran 1D SLAM workloads, and have subsequently published follow-on research that fuses event cameras and radar through spiking neural networks with online STDP learning, with Loihi-class hardware as a target platform.[^13]
- **Robotic control and sensor fusion.** Academic groups in the INRC have used Loihi for low-latency robotic arm control, gesture recognition, neuromorphic skins, and event-based vision pipelines, with recent arXiv preprints (for example, 2024 case studies on sensor fusion in Loihi 2) reporting that Loihi 2 outperforms conventional CPUs and GPUs in energy and latency on these event-driven workloads.[^21]
- **Constrained optimization.** The lava-optimization library exposes solvers for problems such as quadratic unconstrained binary optimization and constraint satisfaction that can be mapped onto neuromorphic primitives, and there is ongoing INRC-funded work on Bayesian optimization, scheduling, and combinatorial search using Loihi 2.[^8]
- **Continual and online learning.** Loihi's on-chip learning engines, augmented by Loihi 2's three-factor rules, are used in studies that aim to update SNN weights in real time as new data arrives, with recent academic work explicitly targeting Loihi 2 for real-time continual learning.[^17]
- **Brain-scale neuroscience simulation.** Hala Point has been positioned by Sandia and Intel as a platform for studying brain-scale spiking networks at meaningful sizes, with neuron counts comparable to small vertebrate brains and a stated target of supporting both AI workloads and computational neuroscience research.[^6][^7]

Intel summarizes the early Loihi 1 benchmarks as "up to 1,000 times faster and 10,000 times more energy efficient than conventional processors" on specialized workloads such as sparse coding, graph search, and constraint satisfaction, with the important caveat that the comparison is workload-specific and tied to event-driven, sparse problem structures rather than dense [deep learning](/wiki/deep_learning) inference.[^13]

## Comparison with other neuromorphic systems

Loihi competes for attention in a small set of large-scale neuromorphic platforms, each of which embodies a different design philosophy. The table below summarizes the most-cited contrasts based on publicly disclosed information from the respective designers.

| System | Designer | Process / substrate | Compute model | Scale per chip | Status |
| --- | --- | --- | --- | --- | --- |
| Loihi 2 | Intel Labs | Pre-production Intel 4 (EUV), digital, asynchronous[^2][^5] | LIF and microcode-programmable spiking neurons; graded spikes; three-factor learning[^5][^9] | Up to 1 M neurons, 120 M synapses, 128 cores[^9] | Research only (INRC)[^10] |
| TrueNorth | IBM Research | 28 nm Samsung CMOS, digital, asynchronous[^22] | Binary spikes, fixed integer LIF; no on-chip learning[^22] | 1 M neurons, 256 M synapses, 4,096 cores[^22] | Research only[^22] |
| SpiNNaker (SpiNNaker 1) | University of Manchester (Steve Furber) | ARM-based many-core (130 nm) digital, asynchronous routing[^23] | ARM cores running software neuron models; selective multicast spike fabric[^23] | 18 ARM cores per chip, hundreds of thousands of neurons[^23] | Operational since 2018 (1 M cores)[^23] |
| Akida (AKD1000) | BrainChip | Commercial CMOS digital[^24] | Event-based convolutional SNN; on-chip incremental learning[^24] | Up to 1.2 M neurons per chip; reported up to 100 B synapses across configurations[^24] | Commercial product[^24] |

The most relevant points of comparison are the following.

IBM's TrueNorth, announced in 2014, also uses 128-like core counts (4,096 cores per chip in TrueNorth's case) and a fully digital, asynchronous, spike-based fabric, but it lacks Loihi's on-chip learning, has fixed integer LIF neurons, and uses binary spikes. Loihi's original IEEE Micro paper explicitly noted that Loihi's 1-bit dense synaptic format provides more than three times higher synaptic density per square millimeter than TrueNorth, and that on-chip programmable learning is a defining differentiator.[^3] IBM has since pivoted to a different generation of brain-inspired silicon, NorthPole, which targets inference rather than spiking neural network training; Loihi 2 remains the only research-grade neuromorphic chip in the digital camp that combines high neuron count, programmable neuron models, and rich on-chip learning.

SpiNNaker (and SpiNNaker 2) takes the opposite approach: it builds neuromorphic systems out of many small general-purpose ARM cores that run user-supplied software neuron models, communicating via a multicast routing fabric. SpiNNaker 1 has been operational at the University of Manchester since 2018 with around one million ARM cores supporting simulations of around one billion neurons.[^23] Independent comparisons published in Neuromorphic Computing and Engineering have found that Loihi is more efficient on simpler spike-based workloads where vector-matrix multiplications are limited, while a SpiNNaker 2 prototype is more efficient on workloads with high-dimensional vector-matrix multiplications, reflecting the contrast between Loihi's dedicated spiking arithmetic and SpiNNaker's programmable ARM cores.[^25]

BrainChip's Akida, in contrast to all of the above, is a commercial neuromorphic IP and ASIC product family. Akida supports event-based convolutional SNNs, on-chip incremental learning, and has been licensed into a range of edge devices targeting milliwatt-class always-on inference. Akida and Loihi share the broad goal of energy-efficient event-driven computation, but they diverge sharply in commercial status (Akida is shipping, Loihi is research-only) and in architectural focus (Akida emphasizes convolutional inference at the edge; Loihi emphasizes flexible spiking primitives for research).[^24]

Within Intel's own portfolio, Loihi sits alongside more conventional AI accelerators such as [Intel Gaudi 3](/wiki/intel_gaudi_3) for transformer-based deep learning, but it is best understood as a research vehicle rather than a competitor to those products. Hala Point, in particular, is positioned as a platform for studying how brain-inspired computing might eventually complement transformer-based AI at scale, not as a deployment target for today's [deep learning](/wiki/deep_learning) workloads.[^6]

## Limitations and criticisms

Loihi has attracted significant attention but remains subject to several well-known caveats, most of which Intel itself has acknowledged in talks and interviews.

First, the chip family is research-only. Intel has consistently stated that Loihi 1 and 2 are not commercial products; access requires INRC membership; and Intel has not announced a productized successor. Critics in the trade press have noted that this restricts deployment and complicates direct comparisons with shipping accelerators.[^10]

Second, neuromorphic computing as a whole still lacks a unified software ecosystem and standard benchmarks. Mike Davies acknowledged in a 2021 IEEE Spectrum interview that "software continues to hold back the field" and that "there hasn't been the emergence of a single software framework as you see in the deep learning world."[^5] Lava is Intel's attempt to address this, but the framework is still maturing and is largely confined to INRC users for the Loihi-specific components.[^8]

Third, the reported efficiency advantages of Loihi are workload-specific. Loihi performs especially well on event-driven, sparse, or constraint-satisfaction problems and on biologically inspired sensor-processing pipelines, but it is not a drop-in replacement for the dense floating-point matrix multiplications that dominate modern transformer-based deep learning. Intel's own descriptions emphasize "specialized" workloads, and independent comparisons with SpiNNaker 2 show that Loihi's advantage is not uniform across all spiking network applications.[^13][^25]

Fourth, programmability is a moving target. Loihi 1's neuron model is essentially fixed leaky-integrate-and-fire with parameterized extensions; Loihi 2 introduces microcoded programmable neurons, but writing custom neuron models still requires expertise in the Loihi microcode and the Lava abstractions, which is a higher barrier than typical [deep learning](/wiki/deep_learning) programming.[^9]

Finally, the field as a whole faces uncertainty about commercial viability. Even Hala Point, with its 1.15 billion neurons and 2,600 W power envelope, represents about one percent of the neuron count of a human brain, and the path from Hala Point-scale research to deployed brain-inspired AI is far from settled.[^6][^7] Trade press coverage has framed Hala Point as both a striking demonstration and an open question about whether neuromorphic approaches can eventually mature into mainstream AI infrastructure.[^7]

## Related work and significance

Loihi is one of the most heavily cited neuromorphic platforms of the late 2010s and early 2020s, and the Davies et al. IEEE Micro paper has accumulated thousands of citations across the neuromorphic, computer architecture, and computational neuroscience communities.[^3] Its significance is twofold. On the hardware side, Loihi demonstrated that a fully digital, asynchronous many-core spiking processor could be designed in a leading-edge process and could scale from a single chip through Pohoiki Beach (64 chips), Pohoiki Springs (768 chips), and Hala Point (1,152 chips) into the billion-neuron regime, all within power envelopes far below those of comparable [GPU](/wiki/gpu) clusters.[^6] On the software and community side, Loihi seeded the INRC and the Lava framework, which together represent one of the largest organized efforts to build a shared infrastructure for neuromorphic algorithm development.[^2][^8]

The platform also serves as a reference point for ongoing debates over the future of AI hardware. As deep learning's energy and dollar costs rise, brain-inspired architectures such as Loihi are frequently cited as one of several candidate "post-Dense-Matrix" paradigms (alongside in-memory computing accelerators, analog photonic accelerators, and emerging memory technologies). Intel and Sandia have explicitly framed Hala Point as a sustainability story, with Mike Davies quoted in the announcement as warning that "the computing cost of today's AI models is rising at unsustainable rates" and positioning neuromorphic systems as one possible response.[^6]

## See also

- [Neuromorphic computing](/wiki/neuromorphic_computing)
- [Neuron](/wiki/neuron)
- [Backpropagation](/wiki/backpropagation)
- [Online learning](/wiki/online_learning)
- [Sparse coding](/wiki/sparse_coding)
- [Lasso regression](/wiki/lasso_regression)
- [Simultaneous localization and mapping (SLAM)](/wiki/slam)
- [Edge computing](/wiki/edge_computing)
- [Edge AI](/wiki/edge_ai)
- [Graphics processing unit](/wiki/gpu)
- [GPU computing](/wiki/gpu_computing)
- [Tensor Processing Unit (TPU)](/wiki/tensor_processing_unit_tpu)
- [Intel Gaudi 3](/wiki/intel_gaudi_3)
- [Cerebras Systems](/wiki/cerebras)
- [Cerebras WSE-3](/wiki/cerebras_wse_3)
- [Groq LPU](/wiki/groq_lpu)
- [Deep Learning](/wiki/deep_learning)
- [Convolutional Neural Network](/wiki/convolutional_neural_network)
- [Neural Network](/wiki/neural_network)
- [LiDAR](/wiki/lidar)
- [DARPA](/wiki/darpa)

## References

[^1]: Intel Corporation, "Intel Editorial: Intel's New Self-Learning Chip Promises to Accelerate Artificial Intelligence", Intel Newsroom, 2017-09-25. https://www.intc.com/news-events/press-releases/detail/202/intel-editorial-intels-new-self-learning-chip-promises. Accessed 2026-05-20.
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