# Ada Lovelace (microarchitecture)

> Source: https://aiwiki.ai/wiki/nvidia_ada_lovelace
> Updated: 2026-06-27
> Categories: AI Hardware, NVIDIA
> From AI Wiki (https://aiwiki.ai), a free encyclopedia of artificial intelligence. Quote with attribution.

**Ada Lovelace** is the graphics processing unit (GPU) microarchitecture that [Nvidia](/wiki/nvidia) announced on September 20, 2022, succeeding the consumer side of the [Ampere](/wiki/nvidia_ampere) architecture and serving as the foundation for the GeForce RTX 40 series of gaming cards and a line of AI inference accelerators led by the [L40S](/wiki/nvidia_l40s). It is fabricated on a custom [TSMC](/wiki/tsmc) "4N" 5 nm-class process, introduces fourth-generation Tensor Cores with FP8 (8-bit floating point) support, third-generation ray tracing (RT) cores, a greatly enlarged on-chip cache, and the DLSS 3 frame-generation technique, and Nvidia rates its flagship AD102 die at up to 1.32 Tensor-petaFLOPS of FP8 throughput.[1][7][10]

Within Nvidia's product lineup, Ada Lovelace is positioned for graphics and AI inference, complementing the [Hopper](/wiki/nvidia_hopper) data center architecture of the same era, which targets large-scale AI training. It powers consumer GeForce RTX 40 cards, the RTX 6000 Ada Generation workstation card, and data center accelerators including the [L40](/wiki/nvidia_l40), L40S, and [L4](/wiki/nvidia_l4). On the consumer side it succeeded Ampere and the earlier Turing generation, and it was succeeded across both consumer and inference-oriented segments by the [Blackwell](/wiki/nvidia_blackwell) architecture, which Nvidia announced at GTC on March 18, 2024.[1][11]

## How is Ada Lovelace named?

The architecture is named after Ada Lovelace (1815 to 1852), the English mathematician and writer often credited as the first computer programmer for her notes on Charles Babbage's proposed Analytical Engine, which included an algorithm intended to be carried out by the machine. The choice continues Nvidia's practice of naming GPU architectures after scientists and mathematicians, following Turing, Ampere, and Hopper. Nvidia and the technical press most often refer to the architecture simply as "Ada Lovelace" or "Ada."[1]

## When was Ada Lovelace announced and launched?

Nvidia chief executive Jensen Huang unveiled the Ada Lovelace architecture during a GTC keynote on September 20, 2022, where he introduced the first GeForce RTX 40 series products.[2][10] "The age of RTX ray tracing and neural rendering is in full steam, and our new Ada Lovelace architecture takes it to the next level," Huang said at the launch.[10] He added that "Ada provides a quantum leap for gamers and paves the way for creators of fully simulated worlds. With up to 4x the performance of the previous generation, Ada is setting a new standard for the industry."[10]

The flagship GeForce RTX 4090 went on sale on October 12, 2022, at a launch price of 1,599 US dollars, followed by the GeForce RTX 4080 (1,199 US dollars for the 16 GB model) in November 2022.[3][10] Data center and professional parts were introduced over the following year: the L40 and the RTX 6000 Ada Generation were announced alongside the consumer launch in 2022, the L4 followed at GTC in March 2023, and the L40S was announced at SIGGRAPH in August 2023.[4][5]

## What are the AD10x dies and the GeForce RTX 40 series?

Ada Lovelace is implemented across a family of dies designated AD102 through AD107, scaling from the flagship desktop part down to entry-level and mobile products. The largest, AD102, contains 76.3 billion transistors on a die of roughly 608 mm2, more than two and a half times the transistor count of the equivalent Ampere die (GA102).[1][6] A fully enabled AD102 provides 18,432 CUDA cores organized into 144 streaming multiprocessors (SMs), with 144 third-generation RT cores and 576 fourth-generation Tensor Cores. Each Ada SM contains 128 CUDA cores, one RT core, four Tensor Cores, and 128 KB of combined shared memory and L1 cache.[1]

The table below summarizes the principal Ada Lovelace dies and the consumer products built on them.

| Die | Transistors | Die size | L2 cache | Example GeForce products |
| --- | --- | --- | --- | --- |
| AD102 | 76.3 billion | ~608 mm2 | 96 MB | RTX 4090 |
| AD103 | 45.9 billion | ~379 mm2 | 64 MB | RTX 4080, RTX 4080 SUPER |
| AD104 | 35.8 billion | ~294 mm2 | 48 MB | RTX 4070 Ti, RTX 4070 |
| AD106 | 22.9 billion | ~188 mm2 | 32 MB | RTX 4060 Ti |
| AD107 | 18.9 billion | ~159 mm2 | (smaller) | RTX 4060 |

The GeForce RTX 4090, the highest-end consumer card, uses a cut-down AD102 with 16,384 CUDA cores, 24 GB of GDDR6X memory on a 384-bit bus delivering about 1,008 GB/s of bandwidth, and a rated total board power of 450 W. Nvidia quoted roughly 82.6 teraFLOPS of FP32 shader throughput for the card.[3][6] The RTX 4080 is built on AD103, and the RTX 4070 family on AD104.[1]

## What architectural advances did Ada Lovelace introduce?

### Larger L2 cache

One of the most consequential changes in Ada Lovelace is a dramatically larger second-level (L2) cache. The full AD102 carries 96 MB of L2 cache, compared with about 6 MB on the Ampere GA102, an increase of roughly 16 times.[6] The larger cache reduces traffic to external memory, which helps Ada parts deliver high effective bandwidth and high clock speeds despite continuing to use conventional GDDR memory rather than [high-bandwidth memory](/wiki/hbm) (HBM). The approach is conceptually similar to the large on-die caches adopted elsewhere in the industry to mitigate the growing gap between compute throughput and memory bandwidth.

### Fourth-generation Tensor Cores and FP8

Ada Lovelace introduced fourth-generation Tensor Cores, the matrix-math units that accelerate AI workloads. The key addition is support for the 8-bit floating-point (FP8) data format through a Transformer Engine, a feature first introduced in the Hopper H100 data center GPU.[7] FP8 roughly doubles arithmetic throughput relative to FP16 for compatible models while keeping accuracy acceptable for many inference tasks, and it can be combined with structural sparsity for further gains. Nvidia states that Ada's Tensor Cores increase throughput by up to five times relative to the previous generation, reaching up to 1.32 Tensor-petaFLOPS of FP8 performance on the highest-end parts, and they support FP8, FP16, bfloat16, and TF32 precisions.[7][10] This capability is central to the architecture's role in generative AI inference, where it is commonly paired with Nvidia's [TensorRT](/wiki/tensorrt) inference software.

### Third-generation RT cores

The third-generation RT cores roughly double ray-triangle intersection throughput compared with Ampere, increasing ray tracing performance by more than two times and reaching up to 191 effective ray-tracing teraFLOPS on the flagship, about 2.8 times the previous generation.[7][10] Two new fixed-function units accompany them. The Opacity Micromap (OMM) Engine accelerates ray tracing of alpha-tested geometry such as foliage, fences, and particles, which previously forced expensive shader work. The Displaced Micro-Mesh (DMM) Engine accelerates construction of the bounding volume hierarchy (BVH) used to organize scene geometry, delivering up to ten times faster BVH build times while using up to twenty times less BVH storage for highly detailed meshes.[7]

### Shader Execution Reordering

Ada introduced Shader Execution Reordering (SER), a scheduling technology that dynamically regroups divergent ray tracing work so that similar shading operations execute together. Nvidia reports that SER can improve shader performance for ray tracing by up to three times and raise in-game frame rates by up to 25 percent.[7]

### DLSS 3 and Frame Generation

Ada Lovelace launched with DLSS 3, which extends Nvidia's Deep Learning Super Sampling upscaling with Frame Generation. Frame Generation uses a dedicated Optical Flow Accelerator together with the fourth-generation Tensor Cores to synthesize entirely new intermediate frames between rendered frames, increasing perceived frame rates. More than 35 games and applications supported the technology at launch.[10] Because it depends on the Optical Flow Accelerator and the new Tensor Cores, full DLSS 3 Frame Generation is exclusive to GeForce RTX 40 series GPUs, while the upscaling and reconstruction components of DLSS remain available on earlier RTX generations.[7]

### Media engine

Ada Lovelace incorporates an eighth-generation NVIDIA Encoder (NVENC) that adds hardware AV1 encoding, which Nvidia describes as roughly 40 percent more efficient than H.264. Higher-end Ada GPUs include dual NVENC encoders that can split a single encoding job to roughly halve export times or encode multiple streams in parallel, a capability that is also valuable for the video-processing workloads targeted by the data center parts.[7]

## What data center and professional products use Ada Lovelace?

While the GeForce parts target gaming and content creation, Nvidia derived a separate line of professional and data center accelerators from the same architecture, all built on the AD102 or AD104 die and all using error-correcting (ECC) GDDR6 memory rather than the GDDR6X found on consumer flagships. These parts emphasize 24-hour duty cycles, passive cooling for server chassis, and AI inference and graphics throughput rather than the highest gaming clocks.

The L40S is the most prominent of these. Announced in 2023, Nvidia calls it "the most powerful universal GPU for the data center," positioned for both AI and graphics and combining strong FP8 inference throughput with the full Ada media and ray tracing feature set.[4] The L40 emphasizes neural graphics, virtualization, and rendering, while the compact, low-power L4 targets high-density video and inference deployments. The RTX 6000 Ada Generation is the corresponding workstation card. Notably, none of the Ada data center parts support [NVLink](/wiki/nvlink); they communicate over PCI Express Gen 4, which reinforces their positioning toward single-GPU inference and visualization rather than the tightly coupled multi-GPU training clusters served by Hopper.

| Product | Die | Memory | Memory bandwidth | FP32 (TFLOPS) | Power | Form factor / target |
| --- | --- | --- | --- | --- | --- | --- |
| L40S | AD102 | 48 GB GDDR6 ECC | 864 GB/s | 91.6 | 350 W | Dual-slot; universal AI and graphics |
| L40 | AD102 | 48 GB GDDR6 ECC | 864 GB/s | ~90 | 300 W | Dual-slot; neural graphics, virtualization |
| L4 | AD104 | 24 GB GDDR6 | 300 GB/s | 30.3 | 72 W | Single-slot, low-profile; video and inference |
| RTX 6000 Ada | AD102 | 48 GB GDDR6 ECC | 960 GB/s | 91.1 | 300 W | Workstation graphics and AI |

The L40S provides 18,176 CUDA cores, 142 third-generation RT cores, and 568 fourth-generation Tensor Cores, with FP8 Tensor throughput of about 733 teraFLOPS (rising to roughly 1,466 teraFLOPS, nearly 1.5 petaFLOPS, with sparsity).[4] Its NVENC and NVDEC media engines support AV1 encode and decode, suiting it to large-scale video pipelines as well as model inference. The L4, by contrast, draws only 72 W in a single-slot, low-profile, passively cooled card, making it well suited to dense server deployments for inference and video transcoding.[8] The RTX 6000 Ada Generation shares the L40-class configuration of 18,176 CUDA cores and 568 Tensor Cores with 48 GB of ECC GDDR6, but is packaged as an active-cooled workstation graphics card.[9]

## What memory and process technology does Ada Lovelace use?

All Ada Lovelace products use GDDR6 or GDDR6X memory rather than HBM. Desktop GeForce flagships such as the RTX 4090 and RTX 4080 use the faster GDDR6X, while the data center and workstation parts use ECC-protected GDDR6.[1][4] The decision to forgo HBM, combined with the very large L2 cache, keeps board costs and power lower than HBM-based designs and aligns the architecture with graphics and inference rather than the memory-bandwidth-bound training workloads that Hopper addresses with HBM2e and HBM3.

The architecture is manufactured on TSMC's "4N" process, a 5 nm-class node customized for Nvidia. This is distinct from TSMC's standard "N4" process and should not be confused with it.[1][6] Nvidia states that the 4N node, coupled with the architectural changes, delivers an up to 2x leap in power efficiency over Ampere, allowing Ada parts to reach substantially higher clock speeds while increasing performance per watt.[10]

## How does Ada Lovelace compare to Ampere and Hopper?

Ada Lovelace occupies a specific niche in Nvidia's portfolio. On the consumer side it succeeded the GeForce RTX 30 series (Ampere) and the earlier RTX 20 series (Turing), advancing real-time ray tracing and AI-assisted rendering. The headline generational gains over Ampere include roughly 16 times more L2 cache, up to 5 times higher Tensor throughput via FP8, more than 2 times the ray tracing performance, and the addition of DLSS 3 Frame Generation, all enabled by the move from Samsung 8 nm (Ampere consumer parts) to the TSMC 4N process.[6][7][10]

On the professional and data center side it coexisted with Hopper, the H100-class architecture launched in the same period. The two architectures are complementary: Hopper, with its HBM memory, NVLink and NVSwitch interconnect, and emphasis on FP8 and FP16 throughput at cluster scale, is built for training and serving the largest AI models, whereas Ada Lovelace targets cost-effective and energy-efficient AI inference, neural graphics, virtual workstations, and video processing. Both architectures were succeeded by Blackwell, which Nvidia describes as the successor to both Hopper and Ada Lovelace.[1][11]

## What is Ada Lovelace's role in AI, and what succeeded it?

The division of labor between Ada and Hopper made Ada-based accelerators, particularly the L40S and L4, popular choices for generative AI inference, recommendation systems, speech and conversational AI, and video analytics during 2023 and 2024, when demand for inference capacity grew sharply alongside the deployment of [large language models](/wiki/large_language_model). The L40S in particular was marketed as a universal accelerator that could handle both inference and lighter training workloads at a lower cost and power envelope than Hopper's H100.[4]

The architecture's successor for both consumer graphics and the inference-oriented professional segment is the [Blackwell](/wiki/nvidia_blackwell) generation, announced at GTC on March 18, 2024, with the consumer GeForce RTX 50 series detailed at CES on January 6, 2025. Blackwell extends the Transformer Engine to a second generation with even lower-precision formats (such as MXFP4 and MXFP6) and is manufactured on a custom TSMC 4NP process, continuing the trajectory of higher AI throughput per watt that Ada Lovelace established for inference.[1][11]

## References

1. Wikipedia, "Ada Lovelace (microarchitecture)." https://en.wikipedia.org/wiki/Ada_Lovelace_(microarchitecture)
2. Tom's Hardware, "Nvidia Announces RTX 4090 Coming October 12, RTX 4080 Later." https://www.tomshardware.com/news/nvidia-geforce-rtx-4090-rtx-4080-price-release-date-specs-revealed
3. TechPowerUp, "NVIDIA GeForce RTX 4090 Specs." https://www.techpowerup.com/gpu-specs/geforce-rtx-4090.c3889
4. NVIDIA, "L40S GPU for AI and Graphics Performance." https://www.nvidia.com/en-us/data-center/l40s/
5. NVIDIA, "L4 Tensor Core GPU for AI & Graphics." https://www.nvidia.com/en-us/data-center/l4/
6. Tom's Hardware, "Nvidia Reveals Ada Lovelace GPU Secrets: Extreme Transistor Counts at High Clocks." https://www.tomshardware.com/news/nvidia-reveals-secrets-of-ada-lovelace-gpus
7. NVIDIA, "Ada Lovelace Architecture." https://www.nvidia.com/en-us/geforce/ada-lovelace-architecture/
8. NVIDIA, "NVIDIA L4 GPU Accelerator Product Brief." https://www.nvidia.com/content/dam/en-zz/Solutions/Data-Center/l4/PB-11316-001_v01.pdf
9. NVIDIA, "RTX 6000 Ada Generation Graphics Card." https://www.nvidia.com/en-us/products/workstations/rtx-6000/
10. NVIDIA Newsroom, "NVIDIA Delivers Quantum Leap in Performance, Introduces New Era of Neural Rendering With GeForce RTX 40 Series" (September 20, 2022). https://nvidianews.nvidia.com/news/nvidia-delivers-quantum-leap-in-performance-introduces-new-era-of-neural-rendering-with-geforce-rtx-40-series
11. Wikipedia, "Blackwell (microarchitecture)." https://en.wikipedia.org/wiki/Blackwell_(microarchitecture)