# TPU Ironwood

> Source: https://aiwiki.ai/wiki/tpu_ironwood
> Updated: 2026-10-15
> Fact-checked: 2026-10-15
> Categories: AI Compute, AI Hardware, AI Infrastructure, Data Centers, Google
> License: CC BY 4.0 (https://creativecommons.org/licenses/by/4.0/) - attribute to "AI Wiki (aiwiki.ai)"
> Cite as: AI Wiki. "TPU Ironwood." aiwiki.ai, 15 Oct 2026. https://aiwiki.ai/wiki/tpu_ironwood
> From AI Wiki (https://aiwiki.ai), the free encyclopedia of artificial intelligence. Reuse freely with attribution.

**TPU Ironwood** (listed as **TPU7x** in Google Cloud's documentation and also called TPU v7) is [Google](https://aiwiki.ai/wiki/google)'s seventh-generation [Tensor Processing Unit](https://aiwiki.ai/wiki/tpu), which Google describes as "the first designed specifically for inference." It was unveiled at Google Cloud Next 2025 in Las Vegas on April 9, 2025.[1][6] On November 6, 2025 Google announced that Ironwood would be generally available in the coming weeks, and its Cloud TPU release notes record TPU7x entering preview on November 24, 2025 and reaching general availability on March 31, 2026.[3][11][19] Each chip delivers 4,614 teraFLOPS of dense FP8 compute (2,307 teraFLOPS at BF16), carries 192 GB of [HBM3E](https://aiwiki.ai/wiki/hbm3e) memory with about 7.37 TB/s of bandwidth, and can be assembled into a superpod of up to 9,216 liquid-cooled chips reaching 42.5 exaFLOPS of aggregate FP8 compute.[1][4][6] Google says that is more than 24 times the compute of El Capitan, which it called the world's largest supercomputer, although the comparison sets Ironwood's FP8 peak against El Capitan's 64-bit benchmark result.[1][6] A full 9,216-chip superpod has 1.77 petabytes of directly accessible [High Bandwidth Memory](https://aiwiki.ai/wiki/high_bandwidth_memory).[2][3] Google says Ironwood is the hardware behind its [Gemini](https://aiwiki.ai/wiki/gemini) models and [Nano Banana](https://aiwiki.ai/wiki/nano_banana), for both training and serving,[2] and it named [Anthropic](https://aiwiki.ai/wiki/anthropic), Lightricks and [Essential AI](https://aiwiki.ai/wiki/essential_ai) as early customers when it announced general availability.[3] In October 2025 Anthropic said it planned to use up to one million Google TPUs in an expansion worth tens of billions of dollars, and in September 2026 [Broadcom](https://aiwiki.ai/wiki/broadcom), which co-designs the chips,[9] said it had delivered Ironwood in high volume to Google and Anthropic.[13][44]

## What is TPU Ironwood?

Ironwood is an application-specific integrated circuit (ASIC) built by Google for running large neural networks at scale, and the seventh generation in the Tensor Processing Unit line that began in 2015. Unlike a general-purpose GPU, it is built around a systolic-array matrix-multiply engine and is offered to customers through [Google Cloud](https://aiwiki.ai/wiki/google_cloud) on [Cloud TPU](https://aiwiki.ai/wiki/cloud_tpu) infrastructure. Google calls Ironwood its first TPU purpose-built for inference and for what it calls the "age of inference," but its documentation describes the Ironwood generation as designed for large-scale AI training as well as inference, and Google markets the chip for pre-training and [reinforcement learning](https://aiwiki.ai/wiki/reinforcement_learning) as well as serving.[1][3][4]

## Background and TPU lineage

Google began designing its first custom AI accelerator in 2013, motivated by a projection that if users interacted with voice search using neural networks for only a few minutes per day, the company would need to double its entire data-center compute capacity to handle the inference load.[15] The solution was an application-specific integrated circuit (ASIC) built around a systolic array optimized for matrix multiplication, rather than a general-purpose GPU.

**TPU v1** entered production in Google data centers in 2015 and was publicly disclosed at Google I/O 2016. Fabricated on a 28 nm process, it contained a 256x256 array of 8-bit multiply-accumulate units delivering roughly 92 TOPS of 8-bit integer performance at 75 W. It was an inference-only accelerator connected to host servers over PCIe 3.0.[14][15]

**TPU v2**, announced in 2017, was the first generation capable of training neural networks. It introduced bfloat16 arithmetic, a 16-bit floating-point format that Google popularized across the AI industry, and 16 GB of HBM memory providing 600 GB/s of bandwidth. Google connected 256 v2 chips into its first TPU pod, with 11.5 petaFLOPS of peak compute.[14][15][19]

**TPU v3**, announced in May 2018, raised per-chip compute from 45 to 123 teraFLOPS (BF16) and introduced liquid cooling, which Google has kept for its performance-class TPUs; XPU.pub notes that the smaller efficiency-oriented models are air-cooled. Pods scaled to 1,024 chips.[10][14][15]

**[TPU v4](https://aiwiki.ai/wiki/google_tpu_v4)**, disclosed in 2021, moved to a 7 nm process and introduced optical circuit switches (OCS) to interconnect chips in a pod without fixed wiring. The OCS fabric allowed any two chips in a pod to communicate through a dynamically reconfigurable optical path, dramatically simplifying large-scale distributed training. TPU v4 pods contained 4,096 chips.[14]

**[TPU v5e](https://aiwiki.ai/wiki/google_tpu_v5e)** and **[TPU v5p](https://aiwiki.ai/wiki/google_tpu_v5p)**, launched in 2023, represented a split into cost-optimized (v5e) and performance-optimized (v5p) variants. TPU v5p carried 95 GB of HBM and delivered 459 teraFLOPS of BF16 compute.[4][14]

**[TPU v6e (Trillium)](https://aiwiki.ai/wiki/google_trillium)**, announced at Google I/O in May 2024 and generally available from December 2024, enlarged the matrix multiply unit from 128x128 to 256x256 multiply-accumulators, raised the clock speed, and delivered 4.7x the peak compute of v5e per chip.[19][29][30] It carried 32 GB of HBM at 1,640 GB/s bandwidth, ran pods of up to 256 chips, and improved energy efficiency by over 67% over v5e.[14][29]

**TPU v7 (Ironwood)**, announced April 2025, is the subject of this article. Its successor, the eighth-generation TPU, was announced in April 2026 as two separate chips: [TPU 8t](https://aiwiki.ai/wiki/google_tpu_8t) for training and [TPU 8i](https://aiwiki.ai/wiki/google_tpu_8i) for inference, both with native FP4 support.[26][27]

## How is Ironwood built?

### Chiplet design

Ironwood is the first Tensor Processing Unit built with more than one compute die: each Ironwood chip packages two compute chiplets.[8] Each chiplet is functionally self-contained: it includes one TensorCore, two SparseCores, and 96 GB of HBM. The two chiplets are joined by a die-to-die (D2D) interface that Google says is six times faster than a single one-dimensional inter-chip interconnect (ICI) link.[4] The design replaces the single logical "MegaCore" used in TPU v4 and v5p: frameworks such as [JAX](https://aiwiki.ai/wiki/jax) expose each Ironwood chip as two devices, one per chiplet, and Google says existing models can be reused with minimal changes.[4]

This gives the assembled chip two TensorCores, four SparseCores, 192 GB of HBM3E across eight stacks, and a combined peak throughput of 4,614 teraFLOPS at FP8.[2][4][8]

The Next Platform, examining photographs of the package at launch, identified further small chiplets that it took to be I/O dies for the inter-chip interconnect; Google has not described them.[7]

[SemiAnalysis](https://aiwiki.ai/wiki/semianalysis) describes Broadcom as the TPU's co-designer and the company through which Google procures the chips.[9] Google has not published Ironwood's process node.

### TensorCore

Each TensorCore contains a Matrix Multiply Unit (MXU) and a Vector Processing Unit (VPU).[2]

The MXU is a 256x256 systolic array of multiply-accumulators, the size Google introduced with Trillium.[30] Ironwood is the first TPU with native FP8 support: Google's launch materials note that FP8 figures for TPU v4 and v5p are emulated, while Ironwood supports the format natively.[1] XPU.pub inferred that Ironwood maps two FP8 operations onto each 16-bit data path, which would make the MXU behave like a 512x512 array at FP8; Google has not published the MXU's internal organization.[10]

The VPU handles element-wise operations such as activations, layer normalizations, and scaling. It runs alongside the MXU to handle the non-matrix portions of typical transformer inference passes.[2]

Google has not published Ironwood's clock speed. Working back from the peak figures, XPU.pub estimated that it runs at about 1.1 GHz, compared with about 1.75 GHz for TPU v5p.[10]

### SparseCore

Each TensorCore is paired with two SparseCores (four total per chip).[4] SparseCore is a specialized dataflow accelerator for the large embedding table lookups that dominate the compute profile of ranking and recommendation systems.[1][30] Google's Hot Chips 2025 presentation described Ironwood's as the fourth generation of SparseCore and said it accelerates collective operations as well as embeddings,[8] and Google said the expanded SparseCore lets Ironwood accelerate workloads beyond the traditional AI domain, in financial and scientific computing.[1]

Google describes SparseCores as handling scalable embedding lookups, which keeps Ironwood relevant for ranking and recommendation serving alongside LLM inference.[1][2]

### AlphaChip co-design

Google used [AlphaChip](https://aiwiki.ai/wiki/alphachip), a reinforcement-learning chip floorplanning method developed by [Google DeepMind](https://aiwiki.ai/wiki/google_deepmind), in designing Ironwood; Google said in November 2025 that AlphaChip had generated layouts for the last three TPU generations, including Ironwood,[5] and its Hot Chips presentation said AI was also used to design arithmetic circuits.[8] DeepMind had said in September 2024 that the earlier AlphaChip-designed generations were TPU v5e, v5p and Trillium, and that the method produces layouts comparable to or better than human designs in hours rather than the weeks or months human engineers need.[35]

## Per-chip specifications

Figures are from Google's documentation and announcements unless noted.[1][4]

| Specification | Value |
|---|---|
| Generation | 7th (TPU7x, also called TPU v7) |
| Codename | Ironwood |
| Architecture | Two compute chiplets per package |
| TensorCores per chip | 2 |
| SparseCores per chip | 4 |
| MXU array size | 256x256 |
| Peak compute (FP8, dense) | 4,614 TFLOPS |
| Peak compute (BF16, dense) | 2,307 TFLOPS |
| HBM type | HBM3E |
| HBM capacity | 192 GB (8 stacks) |
| HBM bandwidth | 7,380 GB/s in Google's documentation (7.37 TB/s at launch) |
| ICI bandwidth | 1,200 GB/s bidirectional (9.6 Tbps) |
| Data center network | 100 Gbps per chip |
| Power per chip | Not published; The Register estimated 700 W to 1 kW[6] |
| Process node | Not published by Google |
| Cooling | Third-generation liquid cooling |
| Host VM | tpu7x-standard-4t: 4 chips, 224 vCPUs, 960 GB RAM |

## How large is an Ironwood pod?

Google offers Ironwood in two standard configurations through Google Cloud: a 256-chip pod and a 9,216-chip superpod.[1] Both are built from 64-chip cubes, four for the pod and 144 for the superpod.[2] The Next Platform described the smaller configuration as suited to inference and the larger to training.[7]

The **9,216-chip superpod** is the largest Ironwood configuration. Google says its 42.5 exaFLOPS of FP8 compute is more than 24 times the 1.7 exaFLOPS of El Capitan at Lawrence Livermore National Laboratory, which Google called the world's largest supercomputer.[1] The Register pointed out that El Capitan's figure is its 64-bit LINPACK result; normalized to FP8, El Capitan's theoretical peak is a little over 87 exaFLOPS.[6] Google notes the full superpod holds 1.77 petabytes of directly addressable HBM across all chips.[2][3] The superpod is slightly larger than a power of two so that it includes spare racks: according to ServeTheHome's report of Google's Hot Chips talk, 8,192 chips would have left no spares.[8]

Google says the superpod spans nearly 10 MW.[1]

For deployments requiring more than 9,216 chips, multiple superpods can be interconnected through Google's data-center network (DCN) using the Jupiter fabric, scaling to hundreds of thousands of chips.[3] A Google spokesperson told The Register in April 2025 that Ironwood could scale beyond a single pod to 400,000 chips, or 43 pods.[6]

The VM configuration for Ironwood in Google Cloud uses the `tpu7x-standard-4t` machine type, which bundles 4 TPU chips with 224 vCPUs and 960 GB of RAM on a full host.[4] This grouping reflects the physical hardware layout: 4 Ironwood chips per liquid-cooled tray and 16 trays per rack (64 chips), paired with separate CPU host racks; connections inside a rack are copper, and optical circuit switches link racks.[8]

### Supported topologies

Within a pod, chips are arranged in a 3D torus topology, and slices larger than 64 chips are built from 4x4x4 cubes. Google's documentation lists common slice shapes from 2x2x1 (4 chips, one host) to 8x16x16 (2,048 chips across 512 hosts), and says the topology allows slices to scale up to 9,216 chips.[4] Larger slices are assembled by connecting cubes through the OCS fabric.[2]

## ICI and networking

### Inter-Chip Interconnect

The Inter-Chip Interconnect (ICI) is a proprietary high-speed link that connects Ironwood chips within a pod. Each chip connects directly to six neighbors in a 3D torus and has 1.2 TB/s (9.6 Tbps) of bidirectional ICI bandwidth.[2][3][4] This represents a 1.5x bandwidth increase over Trillium's ICI.[1]

ICI supports custom remote direct memory access (RDMA), which lets thousands of chips exchange data directly at high bandwidth and low latency without involving the host CPU.[2] This reduces latency for collective operations such as all-reduce and all-gather, which are ubiquitous in distributed training and tensor-parallel inference.

### 3D torus topology

Within a cube of 64 chips, copper ICI links form a 3D torus.[2][30] In this topology, every chip connects to six neighbors (two in each of three spatial dimensions). The torus structure gives each chip multiple paths to every other chip, providing both bandwidth and fault tolerance, and Google says it provides three distinct axes for parallelism.[2]

### Optical circuit switching

Since TPU v4, Google has used Optical Circuit Switches (OCS) to interconnect chip cubes within a pod, and Ironwood continues this approach.[2][14] If a cube or link fails, the OCS fabric manager has the switches bypass the unhealthy unit and set up new optical circuits that connect only healthy cubes, swapping in a designated spare.[2] Google says the fabric routes around interruptions to restore the workload while services keep running,[3] and ServeTheHome reported from Google's Hot Chips talk that a reconfigured slice restores its job from a checkpoint.[8]

For the largest Ironwood clusters, multiple superpods connect through Google's Jupiter data-center network.[3]

## Memory subsystem

Each Ironwood chip carries eight stacks of HBM3E memory, providing 192 GB of capacity and approximately 7.37 TB/s of peak bandwidth.[1][2][8] This is a dramatic increase over previous generations: Trillium (TPU v6e) carried 32 GB at 1,640 GB/s per chip, and TPU v5p carried 95 GB at 2,765 GB/s.[4][14] At 192 GB per chip, Ironwood offers 6 times the HBM capacity of Trillium.[1]

Google says the larger capacity lets customers process larger models and datasets with fewer data transfers.[1] As an illustration, a 70-billion-parameter model stored in BF16 needs roughly 140 GB for its weights alone: at least 5 Trillium chips, but within a single Ironwood chip's 192 GB, which the chip exposes as two 96 GB chiplets.[4]

Google says the 9,216-chip superpod gives 1.77 petabytes of directly accessible HBM.[2][3] The XLA compiler and the Pathways runtime distribute models across those chips.[1][2]

Beyond HBM, each chip has on-chip SRAM, which Google's documentation calls vector memory (VMEM): a high-bandwidth scratchpad next to the MXU whose size is tunable. Engineers manage it directly through the Pallas kernel programming interface, writing custom fused operations that overlap HBM-to-SRAM transfers with MXU computation.[2][4]

Bandwidth compared with prior generations:

| Generation | HBM capacity | HBM bandwidth | Ratio to Trillium (bandwidth) |
|---|---|---|---|
| TPU v5p | 95 GB | 2,765 GB/s | 1.7x |
| TPU v6e (Trillium) | 32 GB | 1,640 GB/s | 1.0x |
| TPU v7 (Ironwood) | 192 GB | 7,370 GB/s | 4.5x |

## How is Ironwood cooled?

Ironwood uses Google's third-generation liquid cooling infrastructure, including third-generation cooling distribution units that supply an Ironwood superpod.[3][8] Liquid cooling was first introduced with TPU v3 in 2018 to handle that generation's higher power density.[14][15]

The chips are cooled by cold plates, and Google uses multiple coolant loops so that the water entering the cold plates stays clean enough not to clog them.[8]

Google says its advanced liquid cooling and chip design can reliably sustain up to twice the performance of standard air cooling under continuous, heavy AI workloads.[1] Google has not published Ironwood's per-chip power; working from the superpod's 10 MW figure, The Register estimated 700 W to 1 kW per chip and XPU.pub about 1 kW.[6][10]

Google says it has deployed liquid cooling at gigawatt scale with fleet-wide uptime of about 99.999% since 2020.[3] Its Hot Chips presentation also described hardware and software features that smooth out megawatt-scale power swings during large training runs, to ease the load on electric utilities.[8]

## How fast is Ironwood?

The following table summarizes Ironwood's key performance figures from Google's announcements and documentation:[1][3][4]

| Metric | Value | Notes |
|---|---|---|
| FP8 peak (per chip) | 4,614 TFLOPS | First TPU generation with native FP8 |
| BF16 peak (per chip) | 2,307 TFLOPS | Standard training precision |
| FP8 peak (9,216-chip superpod) | 42.5 ExaFLOPS | Google's headline figure |
| BF16 peak (9,216-chip superpod) | 21.26 ExaFLOPS | 9,216 x 2,307 TFLOPS |
| HBM bandwidth (per chip) | 7.37 TB/s | 4.5x Trillium |
| HBM capacity (per chip) | 192 GB | 6x Trillium |
| ICI bandwidth (per chip) | 1.2 TB/s bidirectional | 1.5x Trillium |
| Perf/watt vs. Trillium | 2x improvement | Google figure |
| Perf/watt vs. first Cloud TPU (TPU v2, 2018) | Nearly 30x improvement | Peak FP8 FLOPS per watt of TDP per chip package |
| Peak vs. TPU v5p | 10x higher peak TFLOPS | v5p's FP8 rate is emulated at its 459 TFLOPS BF16 rate |
| Per-chip perf vs. Trillium | More than 4x | Training and inference workloads |

Google also says the 9,216-chip superpod has 1.77 petabytes of total addressable HBM and 88,473.6 Tbps (11,059.2 TB/s) of aggregate inter-chip bandwidth.[2][3]

### Benchmarks

As of October 2026, Google had not entered Ironwood in an [MLPerf](https://aiwiki.ai/wiki/mlperf) benchmark round. Its most recent TPU entries were Trillium systems in MLPerf Inference v5.0 (April 2025) and MLPerf Training v5.0 (June 2025), and its entries in the latest rounds, Training v6.0 (June 2026) and Inference v6.1 (September 2026), were NVIDIA GPU systems.[48][49][50][51] XPU.pub noted at Ironwood's launch that Google submits little MLPerf data, which makes direct comparisons with other accelerators harder.[10]

## How does Ironwood compare with Trillium (TPU v6e)?

| Specification | Trillium (TPU v6e) | Ironwood (TPU v7) | Improvement |
|---|---|---|---|
| Peak 8-bit compute | 1,836 TOPS (INT8); 918 TFLOPS (FP8) | 4,614 TFLOPS (FP8) | 2.5x vs. Trillium's INT8 |
| Peak compute (BF16) | 918 TFLOPS | 2,307 TFLOPS | 2.5x per chip |
| HBM capacity | 32 GB | 192 GB | 6x |
| HBM bandwidth | 1,640 GB/s | 7,370 GB/s | 4.5x |
| ICI bandwidth | ~800 GB/s | 1,200 GB/s | 1.5x |
| Max pod size | 256 chips | 9,216 chips | 36x |
| Perf/watt | 1x (baseline) | 2x | 2x |
| Native FP8 | No (FP8 runs at the BF16 rate) | Yes | New |
| Chiplet design | No | Yes (2 dies) | New |
| HBM type | HBM | HBM3E | Newer generation |

Google's documentation lists Trillium's FP8 peak at the same 918 TFLOPS as its BF16 peak; its higher 8-bit figure, 1,836 TOPS, is for INT8 integer arithmetic, and Ironwood is the first TPU generation with native FP8 support.[1][4]

## How does Ironwood compare with NVIDIA Blackwell?

NVIDIA's Blackwell architecture, released in 2024 and 2025 across the B100, B200, and GB200 products, is the primary commercial competitor to Ironwood for large-scale AI inference infrastructure.

| Specification | NVIDIA B200 | NVIDIA GB200 NVL72 | Ironwood (TPU v7) | Ironwood 9,216-chip pod |
|---|---|---|---|---|
| FP8 peak, dense (per accelerator) | 4,500 TFLOPS | 5,000 TFLOPS | 4,614 TFLOPS | n/a |
| HBM capacity | 180 GB (DGX B200) | 186 GB | 192 GB | 1.77 PB |
| HBM bandwidth | 8.0 TB/s | 8.0 TB/s | 7.37 TB/s | n/a |
| Max GPUs/chips per scale-up domain | 8 (HGX/DGX B200) | 72 (NVL72) | 9,216 (superpod) | n/a |
| Interconnect bandwidth | 14.4 Tbps (NVLink) | 14.4 Tbps | 9.6 Tbps (ICI) | n/a |
| FP4 support | Yes | Yes | No | n/a |
| Cooling | Air or liquid | Liquid | Liquid | n/a |
| Third-party ecosystem | Very broad | Very broad | Limited (JAX, PyTorch) | n/a |

NVIDIA figures are from its DGX B200 and GB200 NVL72 specifications, which quote FP8 with sparsity; dense figures are half.[52][53]

Key differences in competitive positioning:

At the per-chip level, Ironwood and NVIDIA's [B200](https://aiwiki.ai/wiki/nvidia_b200) deliver comparable dense FP8 throughput (4,614 vs. 4,500 TFLOPS) and similar HBM capacity (192 GB vs. 180 GB in NVIDIA's DGX B200 specification). NVIDIA's NVLink provides higher per-GPU interconnect bandwidth (14.4 Tbps vs. 9.6 Tbps ICI), and NVIDIA's Blackwell GPUs, including the B300 Blackwell Ultra, support FP4 precision for compressed inference, which Ironwood does not.[10][52][53]

At the pod or cluster level, Google's advantage is scale. Blackwell's largest NVLink domain is 72 GPUs in a single [GB200 NVL72](https://aiwiki.ai/wiki/nvidia_gb200_nvl72) rack. Ironwood is purpose-built to operate as 9,216 chips in a single ICI and optical-switch domain, and XPU.pub argued that this could give it an advantage as systems scale, since NVIDIA has to turn to InfiniBand or Ethernet beyond 72 GPUs.[10][53]

On total cost of ownership, SemiAnalysis estimated in November 2025 that, for Google's own use, the all-in cost per Ironwood chip in a full 3D torus configuration is about 44% lower than that of an equivalent GB200 server, and that for external customers renting through Google Cloud the cost per hour can still be up to about 30% lower than GB200 and about 41% lower than GB300.[9]

## Software stack

### Compiler: XLA

All Ironwood workloads compile through [XLA](https://aiwiki.ai/wiki/xla) (Accelerated Linear Algebra), Google's domain-specific compiler for tensor programs. XLA ingests programs written in JAX or PyTorch, performs whole-program optimization including operator fusion, operation scheduling, and layout selection, then emits optimized TPU machine code. XLA's whole-program view lets it make decisions that per-operator compilers cannot, such as fusing a sequence of matrix multiplications, activations, and normalizations into a single kernel that avoids repeated round trips to HBM.[2]

### JAX

JAX is the primary framework for Ironwood. JAX programs are Python expressions that describe tensor computations using NumPy-like syntax. The `jit` decorator triggers XLA compilation. The `grad` function computes exact gradients via reverse-mode automatic differentiation, enabling training without manually writing backward passes. The `shard_map` primitive allows explicit specification of how tensors are partitioned across a mesh of chips.[2]

Google DeepMind and other Google teams use JAX to build, train and serve their models. MaxText, an open-source LLM framework from Google written in JAX, supports pre-training and post-training on Ironwood, including supervised fine-tuning and reinforcement learning techniques such as GRPO, with reference implementations of open models such as DeepSeek, Qwen, gpt-oss and Gemma.[2][3]

The JAX ecosystem for Ironwood includes several production-grade libraries:[2]

| Library | Purpose |
|---|---|
| Optax | Gradient processing and optimization algorithms (AdamW, Lion, etc.) |
| Orbax | Asynchronous distributed checkpointing for large model arrays |
| Qwix | Quantization-aware training and post-training quantization |
| Metrax | Distributed evaluation metric computation |
| Tunix | Post-training pipeline orchestration |
| Goodput | ML training efficiency measurement and monitoring |

### PyTorch

When it announced general availability, Google said it was developing a new native [PyTorch](https://aiwiki.ai/wiki/pytorch) experience for TPUs, with full eager mode, the standard `torch.distributed` APIs built on DTensor, and `torch.compile` using XLA as its backend, so that PyTorch users could move models to Ironwood with minimal code changes.[2] Reuters reported in December 2025 that the effort, known internally as TorchTPU, was being developed with help from Meta, the steward of PyTorch.[36] In April 2026 Google said native PyTorch support for TPUs was in preview, and that the same JAX, PyTorch or Keras code that runs on Ironwood would carry over to its eighth-generation TPUs.[27] Earlier, PyTorch reached TPUs through the PyTorch/XLA library.[19]

[vLLM](https://aiwiki.ai/wiki/vllm), the popular open-source LLM serving framework, has a TPU backend that works with Ironwood. The `tpu-inference` plugin provides a unified JAX/PyTorch lowering path for inference, and Google's TPU7x documentation lists vLLM serving recipes that use optimized PagedAttention kernels.[2][4]

### Pallas

Pallas is a domain-specific language embedded in JAX for writing custom TPU kernels. It provides explicit control over the HBM-to-SRAM data movement pipeline and allows engineers to overlap memory transfers with MXU computation. Mosaic, Pallas's compiler backend, handles tiling, operator fusion, and software pipelining to produce optimized TPU machine code. Pallas is used for custom attention kernels, mixture-of-experts optimizations, and other operations where XLA's automatic optimization falls short of theoretical peak.[2]

### Pathways

[Pathways](https://aiwiki.ai/wiki/pathways) is Google's distributed ML runtime, originally developed by Google DeepMind, which lets developers combine the computing power of many TPU chips; Google says it can compose hundreds of thousands of Ironwood chips and gives TPU users capabilities such as elastic training and multi-host inference during reinforcement learning.[1][2] Google says MaxText relies on Pathways and handles fault tolerance and checkpointing transparently for jobs at superpod scale.[2]

Google's documentation lists JAX and PyTorch as the frameworks that run on TPU7x; TensorFlow is not supported.[4]

## How do you access Ironwood?

Google's documentation lists Google Kubernetes Engine (GKE) and Compute Engine as the ways to use TPU7x. GKE customers can also reserve Ironwood in All Capacity mode, which gives full access to the reserved capacity and visibility into the hardware topology, utilization and health.[4] Compute Engine's APIs for creating and managing TPU VMs and slices became generally available on June 1, 2026.[19]

Ironwood was announced at Google Cloud Next on April 9, 2025, when Google said it would become available later that year.[1][6] On November 6, 2025 Google announced that Ironwood would be generally available in the coming weeks and invited customers to sign up to test it.[3][11]

In Google Cloud's release notes, TPU7x is recorded as entering preview on November 24, 2025 and reaching general availability on March 31, 2026.[19] The Next Web reported Ironwood as generally available to cloud customers at Google Cloud Next 2026 in Las Vegas in April 2026, the same event at which Google previewed the chip's eighth-generation successors.[18]

TPU7x runs on the `tpu7x-standard-4t` VM shape: 4 TPU chips, 224 vCPUs, 960 GB RAM per VM.[4] Storage uses Hyperdisk Balanced by default, with Hyperdisk ML also supported.[4] Boot and attached disks use Google's standard Hyperdisk infrastructure.

In October 2026 Google's zone list showed TPU7x only in the us-central1 region, in zone us-central1-c and the AI zone us-central1-ai1a; AI zones, which Cloud TPU began supporting in April 2026, are specialized zones for AI workloads located near standard Google Cloud zones.[19][34]

Google's pricing page began listing Ironwood in early 2026. A March 9, 2026 archived copy shows an on-demand rate of $12.00 per chip-hour in us-central1 (Iowa), $8.40 with a one-year commitment and $5.40 with a three-year commitment, and $13.20 on demand in europe-west2 (London).[33] The same rates were listed in October 2026, alongside $6.00 per chip-hour for Dynamic Workload Scheduler (DWS) Flex-start capacity and $8.40 in DWS calendar mode; on October 16, 2026, Google's Spot price list showed TPU7x at about $4.12 per chip-hour in us-central1.[31][32]

Google also brought its Cluster Director capabilities, including advanced maintenance and topology awareness for scheduling, to TPU customers on GKE.[3] GKE's Inference Gateway load-balances requests across TPU servers, which Google says cuts time-to-first-token latency by up to 96% and serving costs by up to 30%.[3]

## What does Google use Ironwood for?

### Gemini models

Google said in November 2025 that Ironwood is "the cutting-edge hardware behind advanced models like Gemini and Nano Banana, from massive-scale training to high-throughput, low-latency inference."[2] Google says Ironwood's memory and compute are tuned for both the large-batch prefill phase and the memory-bandwidth-intensive decode phase of large generative models, including reasoning models.[1][2]

### AlphaFold and DeepMind research

At the April 2025 launch, Google said that Gemini 2.5 and the Nobel Prize-winning [AlphaFold](https://aiwiki.ai/wiki/alphafold) already ran on TPUs, without tying either to a particular TPU generation.[1] Google has not published a full list of the internal workloads that run on Ironwood.

## Which companies use Ironwood?

### Anthropic

Anthropic announced on October 23, 2025 that it planned to expand its use of Google Cloud technologies, including up to one million TPUs, in an expansion worth tens of billions of dollars that it expected to bring well over a gigawatt of capacity online in 2026.[13] Google Cloud CEO Thomas Kurian said the decision reflected "the strong price-performance and efficiency" Anthropic's teams had seen with TPUs for several years, and pointed to Ironwood.[13] When announcing Ironwood's general availability, Google said Anthropic was drawn by its price-performance gains, and Anthropic's head of compute, James Bradbury, said Ironwood's improvements in inference performance and training scalability would help the company scale efficiently.[3]

Krishna Rao, Anthropic's chief financial officer, framed the deal around customer demand, saying that Anthropic's customers "depend on Claude for their most important work."[13] SemiAnalysis reported in November 2025 that the first phase of the deal covered 400,000 Ironwood chips, worth about $10 billion as finished racks that Broadcom would sell directly to Anthropic, and estimated that the remaining 600,000 would be rented through Google Cloud.[9] In September 2026 Broadcom CEO Hock Tan described a one-gigawatt Ironwood deployment for Anthropic in 2026.[43][44]

On April 6, 2026, Anthropic signed a further agreement with Google and Broadcom for multiple gigawatts of next-generation TPU capacity starting in 2027. Broadcom's securities filing said Anthropic would access about 3.5 gigawatts of it through Broadcom, depending on Anthropic's continued commercial success, and Anthropic later described the agreement as 5 gigawatts.[39][40][41] On April 24, 2026, Google committed $10 billion in cash to Anthropic and up to $30 billion more if Anthropic met performance targets.[42] The [Anthropic-Google TPU deal](https://aiwiki.ai/wiki/anthropic_google_tpu_deal) article covers these agreements in detail.

### Lightricks

Lightricks, the maker of AI-based creative tools, said in November 2025 that it had relied on Google Cloud TPUs and their large ICI domain to train its open-source LTX-2 multimodal generative model, and that its early testing of Ironwood made it "highly enthusiastic" about the chip for image and video generation.[3][12]

### Essential AI

Essential AI, which builds open frontier models, said Ironwood's platform was "incredibly easy to onboard."[3]

### Meta

In November 2025, The Information reported that [Meta](https://aiwiki.ai/wiki/meta_ai) was in talks to spend billions of dollars on Google TPUs for its own data centers from 2027 and to rent TPU capacity through Google Cloud as early as 2026; some Google Cloud executives reportedly suggested that the strategy of putting TPUs in customers' data centers could capture as much as 10% of [NVIDIA](https://aiwiki.ai/wiki/nvidia)'s annual revenue.[21][38] The report lifted Alphabet shares and weighed on NVIDIA's, prompting NVIDIA to post a public statement saying it was "delighted by Google's success" while asserting that NVIDIA remained "a generation ahead of the industry."[22][23]

In December 2025 Reuters reported that Google was working closely with Meta on TorchTPU, its effort to make TPUs run PyTorch natively.[36] On February 26, 2026, The Information reported that Meta had signed a multi-year, multibillion-dollar deal to rent Google's TPUs and was still in talks to buy TPUs for its own data centers; Meta and Google declined to comment.[37] As of October 2026 neither company had publicly confirmed the arrangement.

## 2025-2026 developments

### Gemini 3

Google DeepMind released [Gemini 3](https://aiwiki.ai/wiki/gemini_3) on November 18, 2025, shortly after the Ironwood general-availability announcement. The Gemini 3 Pro model card states that the model was trained using Google's Tensor Processing Units, with JAX and ML Pathways, without naming a TPU generation.[20] A CNBC Investing Club analysis noted that Gemini 3 had been trained entirely on TPUs and called the launch a wake-up call for AI investors, while still recommending NVIDIA shares.[23]

### TPUs in third-party data centers

In September 2025, The Information reported that Google had begun placing TPUs in data centers operated by other cloud providers for the first time, agreeing to install chips at a [Fluidstack](https://aiwiki.ai/wiki/fluidstack) site in New York and approaching other providers, including [CoreWeave](https://aiwiki.ai/wiki/coreweave) and Crusoe, about hosting TPUs.[24] Google supported the associated buildout financially: by August 2025 it had agreed to backstop approximately $3.2 billion of Fluidstack's lease obligations at TeraWulf's Lake Mariner campus in western New York, in exchange for warrants representing a pro forma equity stake of approximately 14% in TeraWulf.[25]

Alphabet said in April 2026 that it would begin delivering TPUs to a select group of customers in their own data centers, and in July 2026 that it had delivered TPU systems to customer data centers for the first time in the second quarter.[45][46] In May 2026 Blackstone announced a joint venture with Google to offer Google Cloud TPUs as a service from new data centers, with $5 billion of initial equity and the first 500 MW of capacity expected online in 2027.[47] The Cloud TPU article covers these distribution channels in more detail.

### Eighth-generation successors

At Google Cloud Next 2026 on April 22, 2026, Google previewed the two chips that succeed Ironwood: TPU 8t, optimized for large-scale training, and TPU 8i, optimized for serving and agentic inference.[26][28] Google published per-chip figures of 12.6 petaFLOPS of FP4 compute, 216 GB of HBM and 6,528 GB/s of memory bandwidth for TPU 8t, against 10.1 petaFLOPS of FP4 compute, 288 GB of HBM and 8,601 GB/s for TPU 8i; both chips are rated at up to 2x Ironwood's performance per watt.[27] TPU 8t superpods grow to 9,600 chips (121 FP4 exaFLOPS), and the new [Virgo](https://aiwiki.ai/wiki/google_virgo_network) network fabric can link more than 134,000 TPU 8t chips in a single non-blocking fabric.[26][27] Google said TPU 8t delivers up to 2.7x better performance per dollar than Ironwood for large-scale training, and TPU 8i up to 80% better performance per dollar for low-latency inference of large mixture-of-experts models.[27]

Both eighth-generation chips run on Google's own Arm-based [Axion](https://aiwiki.ai/wiki/google_axion) host CPUs, which Google said was a first for its TPUs; Tom's Hardware reported that they replace the x86 hosts of earlier generations.[26][28] Google said both chips would be generally available later in 2026,[26] but in October 2026 its documentation still described TPU7x as the latest TPU available on Google Cloud.[4] It is the first time Google has split a TPU generation into separate training and inference chips.[28] Trade press reported that Broadcom designed TPU 8t and [MediaTek](https://aiwiki.ai/wiki/mediatek) TPU 8i, and The Next Web gave their codenames as Sunfish and Zebrafish; Google did not name the design partners.[18][28] In September 2026 Broadcom said it had begun production shipments of TPU 8i to Google and expected Anthropic to deploy another 5 gigawatts of TPU 8i in 2027.[43][44]

## See also

- [Cloud TPU](https://aiwiki.ai/wiki/cloud_tpu)
- [Anthropic-Google TPU deal](https://aiwiki.ai/wiki/anthropic_google_tpu_deal)
- [Google Virgo Network](https://aiwiki.ai/wiki/google_virgo_network)
- [Tensor Processing Unit](https://aiwiki.ai/wiki/tpu)
- [TPU Pod](https://aiwiki.ai/wiki/tpu_pod)
- [Trillium (TPU v6e)](https://aiwiki.ai/wiki/google_trillium)
- [Google DeepMind](https://aiwiki.ai/wiki/google_deepmind)
- [Vertex AI](https://aiwiki.ai/wiki/google_vertex_ai)
- [JAX](https://aiwiki.ai/wiki/jax)
- [Google](https://aiwiki.ai/wiki/google)
- [Google Cloud](https://aiwiki.ai/wiki/google_cloud)
- [NVIDIA H100](https://aiwiki.ai/wiki/nvidia_h100)
- [NVIDIA Blackwell](https://aiwiki.ai/wiki/nvidia_blackwell)

## References

1. Google Blog. "Ironwood: The first Google TPU for the age of inference." April 9, 2025. https://blog.google/innovation-and-ai/infrastructure-and-cloud/google-cloud/ironwood-tpu-age-of-inference/
2. Google Cloud Blog. "Inside the Ironwood TPU codesigned AI stack." November 6, 2025. https://cloud.google.com/blog/products/compute/inside-the-ironwood-tpu-codesigned-ai-stack
3. Google Cloud Blog. "Ironwood TPUs and new Axion-based VMs for your AI workloads." November 7, 2025. https://cloud.google.com/blog/products/compute/ironwood-tpus-and-new-axion-based-vms-for-your-ai-workloads
4. Google Cloud Documentation. "TPU7x (Ironwood)." https://docs.cloud.google.com/tpu/docs/tpu7x
5. Google Blog. "3 things to know about Ironwood, Google's latest TPU." November 25, 2025. https://blog.google/innovation-and-ai/infrastructure-and-cloud/google-cloud/ironwood-google-tpu-things-to-know/
6. The Register. "Google's 7th-gen Ironwood TPUs promise 42 AI exaFLOPS pods." April 10, 2025. https://www.theregister.com/2025/04/10/googles_7thgen_ironwood_tpus_debut/
7. The Next Platform. "With Ironwood TPU, Google Pushes The AI Accelerator To The Floor." April 9, 2025. https://www.nextplatform.com/compute/2025/04/09/with-ironwood-tpu-google-pushes-the-ai-accelerator-to-the-floor/1660461
8. ServeTheHome. "Google Ironwood TPU Swings for Reasoning Model Leadership at Hot Chips 2025." August 27, 2025. https://www.servethehome.com/google-ironwood-tpu-swings-for-reasoning-model-leadership-at-hot-chips-2025/
9. SemiAnalysis. "Google TPUv7: The 900lb Gorilla In the Room." November 28, 2025. https://newsletter.semianalysis.com/p/tpuv7-google-takes-a-swing-at-the
10. XPU.pub. "Google Adds FP8 to Ironwood TPU; Can It Beat Blackwell?" April 16, 2025. https://xpu.pub/2025/04/16/google-ironwood/
11. CNBC. "Google unveils Ironwood, seventh generation TPU, competing with Nvidia." November 6, 2025. https://www.cnbc.com/2025/11/06/google-unveils-ironwood-seventh-generation-tpu-competing-with-nvidia.html
12. VentureBeat. "Google debuts AI chips with 4X performance boost, secures Anthropic megadeal worth billions." November 6, 2025. https://venturebeat.com/infrastructure/google-debuts-ai-chips-with-4x-performance-boost-secures-anthropic-megadeal
13. Anthropic. "Expanding our use of Google Cloud TPUs and Services." October 23, 2025. https://www.anthropic.com/news/expanding-our-use-of-google-cloud-tpus-and-services
14. Wikipedia. "Tensor Processing Unit." https://en.wikipedia.org/wiki/Tensor_Processing_Unit
15. Google Cloud Blog. "TPU transformation: A look back at 10 years of our AI-specialized chips." https://cloud.google.com/transform/ai-specialized-chips-tpu-history-gen-ai
16. TrendForce. "Google Unveils 7th-Gen TPU Ironwood with 9,216-Chip Superpod, Taking Aim at NVIDIA." November 7, 2025. https://www.trendforce.com/news/2025/11/07/news-google-unveils-7th-gen-tpu-ironwood-with-9216-chip-superpod-taking-aim-at-nvidia/
17. Tom's Hardware. "Google deploys new Axion CPUs and seventh-gen Ironwood TPU." 2025. https://www.tomshardware.com/tech-industry/artificial-intelligence/google-deploys-new-axion-cpus-and-seventh-gen-ironwood-tpu-training-and-inferencing-pods-beat-nvidia-gb300-and-shape-ai-hypercomputer-model
18. The Next Web. "Google splits its next TPU in two, and the AI chip war just became a design philosophy fight." April 22, 2026. https://thenextweb.com/news/google-ironwood-tpu-inference-cloud-next
19. Google Cloud Documentation. "Cloud TPU release notes." https://docs.cloud.google.com/tpu/docs/release-notes
20. Google DeepMind. "Gemini 3 Pro Model Card." November 2025. https://storage.googleapis.com/deepmind-media/Model-Cards/Gemini-3-Pro-Model-Card.pdf
21. TrendForce. "Meta Reportedly Weighs Google TPU Deployment in 2027, Boosting Broadcom, Taiwan's GUC." November 25, 2025. https://www.trendforce.com/news/2025/11/25/news-meta-reportedly-weighs-google-tpu-deployment-in-2027-boosting-broadcom-taiwans-guc/
22. Tom's Hardware. "Google TPUs garner attention as AI chip alternative, but are only a minor threat to Nvidia's dominance - Alphabet's biggest challenge is widespread adoption." November 26, 2025. https://www.tomshardware.com/tech-industry/semiconductors/nvidia-responds-as-meta-explores-switch-to-google-tpus
23. CNBC. "Gemini 3 - and the custom chips that power it - is a wake up call for AI investors." November 25, 2025. https://www.cnbc.com/2025/11/25/gemini-3-and-the-custom-chips-that-train-it-is-a-wake-up-call-for-ai-investors.html
24. Business Standard. "Google pushes its AI chips into rival data centres, challenging Nvidia." September 8, 2025. https://www.business-standard.com/world-news/google-tpus-challenge-nvidia-ai-chips-cloud-data-centres-125090800159_1.html
25. TeraWulf. "TeraWulf Announces Fluidstack Expansion with 160 MW CB-5 Lease at Lake Mariner." August 18, 2025. https://www.sec.gov/Archives/edgar/data/1083301/000110465925079463/tm2523651d3_ex99-1.htm
26. Google Blog. "Our eighth generation TPUs: two chips for the agentic era." April 22, 2026. https://blog.google/innovation-and-ai/infrastructure-and-cloud/google-cloud/eighth-generation-tpu-agentic-era/
27. Google Cloud Blog. "TPU 8t and TPU 8i technical deep dive." April 23, 2026. https://cloud.google.com/blog/products/compute/tpu-8t-and-tpu-8i-technical-deep-dive
28. Tom's Hardware. "Inside Google's TPU V8 strategy, delivering two chips for two crucial tasks at incredible scale - network scales up to 1 million TPUs per cluster, an advantage over Nvidia AI accelerators." April 27, 2026. https://www.tomshardware.com/tech-industry/semiconductors/google-splits-its-tpu-into-two-chips-for-the-first-time-with-training-and-inference-variants
29. Google Cloud Blog. "Trillium, the sixth generation of Google Cloud TPU." May 2024. https://cloud.google.com/blog/products/compute/introducing-trillium-6th-gen-tpus
30. Google Cloud Documentation. "TPU architecture." Google Cloud, 2026-10-13. https://docs.cloud.google.com/tpu/docs/system-architecture-tpu-vm
31. Google Cloud. "Cloud TPU pricing." Google Cloud, 2026-10-16. https://cloud.google.com/tpu/pricing
32. Google Cloud. "Spot VMs pricing." Google Cloud, 2026-10-16. https://cloud.google.com/spot-vms/pricing
33. Internet Archive. "Cloud TPU pricing (archived copy)." Internet Archive, 2026-03-09. https://web.archive.org/web/20260309161836/https://cloud.google.com/tpu/pricing
34. Google Cloud Documentation. "TPU regions and zones." Google Cloud, 2026-10-13. https://docs.cloud.google.com/tpu/docs/regions-zones
35. Google DeepMind. "How AlphaChip transformed computer chip design." Google DeepMind, 2024-09-26. https://deepmind.google/discover/blog/how-alphachip-transformed-computer-chip-design/
36. Reuters. "Google works to erode Nvidia's software advantage with Meta's help." TimesLIVE, 2025-12-18. https://www.timeslive.co.za/news/sci-tech/2025-12-18-google-works-to-erode-nvidias-software-advantage-with-metas-help/
37. Reuters. "Meta signs multi-billion-dollar deal to rent Google AI chips, The Information reports." The Standard, 2026-02-27. https://www.thestandard.com.hk/tech-and-startup/article/325426/Meta-signs-multi-billion-dollar-deal-to-rent-Google-AI-chips-The-Information-reports/
38. Reuters. "Meta in talks to spend billions on Google's chips, The Information reports." Business Reporter, 2025-11-25. https://www.business-reporter.co.uk/news/meta-in-talks-to-spend-billions-on-googles-chips-the-information-reports-13758
39. Anthropic. "Anthropic expands partnership with Google and Broadcom for multiple gigawatts of next-generation compute." Anthropic, 2026-04-06. https://www.anthropic.com/news/google-broadcom-partnership-compute
40. Broadcom Inc. "Current Report on Form 8-K (Item 8.01)." U.S. Securities and Exchange Commission, 2026-04-06. https://www.sec.gov/Archives/edgar/data/1730168/000119312526144028/d87999d8k.htm
41. Anthropic. "Higher usage limits and a SpaceX compute deal." Anthropic, 2026-05-06. https://www.anthropic.com/news/higher-limits-spacex
42. Reuters. "Google to invest up to US$40B in AI rival Anthropic." BNN Bloomberg, 2026-04-24. https://www.bnnbloomberg.ca/business/company-news/2026/04/24/google-to-invest-up-to-us40b-in-ai-rival-anthropic/
43. SDxCentral. "Broadcom slams AI silicon-fueled Q3, promises double-double on the way." SDxCentral, 2026-09-03. https://www.sdxcentral.com/news/broadcom-slams-ai-silicon-fueled-q3-promises-double-double-on-the-way/
44. Benzinga. "Broadcom CEO Hock Tan Says Anthropic 'On Track to Become Our Largest XPU Customer' as Google TPU Orders Explode." Webull, 2026-09-03. https://www.webull.com/news/15513120997254144
45. Alphabet. "Q1 2026 Earnings Call Transcript." Alphabet Investor Relations, 2026-04-29. https://s206.q4cdn.com/479360582/files/doc_events/2026/Apr/29/2026_Q1_Earnings_Transcript.pdf
46. Alphabet. "Q2 2026 Earnings Call Transcript." Alphabet Investor Relations, 2026-07-22. https://s206.q4cdn.com/479360582/files/doc_events/2026/Jul/22/2026_Q2_Earnings_Transcript.pdf
47. Blackstone. "Blackstone Announces Joint Venture with Google to Create New TPU Cloud." Business Wire, 2026-05-18. https://www.businesswire.com/news/home/20260518367552/en/Blackstone-Announces-Joint-Venture-with-Google-to-Create-New-TPU-Cloud
48. MLCommons. "MLPerf Inference v5.0 results: Google closed-division systems." MLCommons, 2025-04-01. https://github.com/mlcommons/inference_results_v5.0/tree/main/closed/Google/systems
49. MLCommons. "MLPerf Training v5.0 results: Google systems." MLCommons, 2025-05-30. https://github.com/mlcommons/training_results_v5.0/tree/main/Google/systems
50. MLCommons. "MLPerf Training v6.0 results: Google systems." MLCommons, 2026-06-15. https://github.com/mlcommons/training_results_v6.0/tree/main/Google/systems
51. MLCommons. "MLPerf Inference v6.1 results: Google closed-division systems." MLCommons, 2026-09-14. https://github.com/mlcommons/inference_results_v6.1/tree/main/closed/Google/systems
52. NVIDIA. "NVIDIA DGX B200." NVIDIA, 2026-10-16. https://www.nvidia.com/en-us/data-center/dgx-b200/
53. NVIDIA. "NVIDIA GB200 NVL72." NVIDIA, 2026-10-16. https://www.nvidia.com/en-us/data-center/gb200-nvl72/


---

## Live data: TPU v7 (Ironwood) specifications

> Generated from AI Compute Tracker (https://aicomputetracker.com/accelerators.json), not part of the article text. Specs reviewed 2026-10-15. AI Compute Tracker is a companion site owned and operated by the same team as AI Wiki. Data: AI Compute Tracker (aicomputetracker.com), CC BY 4.0; third-party terms apply to data from Chip vendor documentation.

- Google TPU v7 (Ironwood), availability: shipping, first availability 2025-11.
- Dense FP16/BF16: 2,307 TFLOPS
- Dense FP8: 4,614 TFLOPS
- Memory: 192 GiB
- Bandwidth: 7.38 TB/s
- Interconnect: ICI · 9,216-chip pods

More: https://aicomputetracker.com/hardware/