AMD Instinct MI400

AMD Instinct MI400 is AMD's 2026 family of data center GPU accelerators for artificial intelligence training and inference, built on the CDNA 5 architecture. The flagship AMD Instinct MI455X carries 432 GB of HBM4 memory, 23.3 TB/s of peak memory bandwidth, and up to 40.26 PFLOPS of peak MXFP4 compute. AMD first previewed the series at Advancing AI 2025 in San Jose on 2025-06-12, named the individual parts at CES on 2026-01-06, and formally launched the family at Advancing AI 2026 in San Francisco on 2026-07-22 and 2026-07-23. The launch lineup is the MI455X for frontier AI training and inference and the MI430X for HPC and sovereign AI; a third part, the MI440X for enterprise AI servers, was disclosed at CES but did not appear in the July launch materials. The series succeeds the MI350 generation, whose top part is the AMD Instinct MI355X.^[1][3][4][8]

The MI400 series anchors AMD's first complete rack-scale AI system, Helios, which couples 72 MI455X accelerators with next-generation EPYC "Venice" Zen 6 CPUs and Pensando "Vulcano" 800 Gb/s NICs in a double-wide Open Compute Project rack. Helios is AMD's answer to NVIDIA's Vera Rubin platform, and it is the hardware foundation for two of the largest non-NVIDIA compute commitments signed to date: a 6 gigawatt agreement with OpenAI announced on 2025-10-06, and a commitment from Anthropic announced on 2026-07-22 covering up to 2 gigawatts.^[7][15][16] Every performance figure AMD has published for the series comes from AMD Performance Labs; as of 2026-07-27 no independent benchmark of MI400 silicon had been published, and AMD had not disclosed board power or pricing for any MI400 part.^[11][12]

Announcement and launch timeline

AMD first publicly committed to the MI400 series at Advancing AI 2025 in San Jose, California on 2025-06-12. During the keynote, AMD chair and CEO Lisa Su outlined a multi-year accelerator roadmap that included the just-launched MI350 series, the MI400 series for 2026, and a follow-on MI500 generation for 2027. AMD framed the MI400 launch as the moment when its data center GPU business would transition from selling individual accelerators to selling complete rack-scale systems on equal footing with NVIDIA's GB200 NVL72 and the forthcoming Vera Rubin rack.^[17][28]

The named product family arrived at CES on 2026-01-06, when AMD introduced three variants (MI430X, MI440X, MI455X), confirmed the Helios reference design, showed working silicon in a Helios compute tray for the first time, and previewed an MI500 generation for 2027.^[18][19][24]

The formal launch came at Advancing AI 2026 in San Francisco on 2026-07-22 and 2026-07-23. AMD's launch press release announced the MI455X and the MI430X, the Helios rackscale solution, the MI350P, and a software initiative called ROCm.ai. The MI440X was not mentioned in AMD's launch release and has no AMD product page.^[1][3]

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MI400 Series or MI450 Series?

AMD's own materials from launch week do not use a single family name. The Advancing AI 2026 press release and the AMD product pages call the family the "AMD Instinct MI400 Series."^[1][4] The Anthropic partnership release, issued one day earlier, is titled "AMD and Anthropic Announce Strategic Partnership to Deploy Up to 2 Gigawatts of AMD Instinct MI450 Series GPUs" and refers throughout to the "MI450 Series."^[15] Both documents identify the same silicon, the MI455X, as the part being deployed. The October 2025 OpenAI release likewise used "MI450 Series."^[16] AMD has not published a statement reconciling the two names, and this article uses MI400 series to match the product pages.

Architecture

CDNA 5

The MI400 series is the first product family built on AMD's CDNA 5 (Compute DNA, fifth generation) GPU architecture. CDNA 5 drops graphics rasterization entirely in favor of denser AI and HPC math units, and it is AMD's most aggressive chiplet design to date, combining dies from two TSMC process nodes inside a single package.^[9][20]

The MI455X package integrates eight accelerator complex dies (XCDs) built on TSMC N2, plus two I/O dies and two fabric and cache dies on N3, assembled with TSMC CoWoS-L packaging. AMD puts the total at roughly 320 billion transistors. The design exposes 256 work group processors, runs to a 2.4 GHz maximum engine clock, and carries 192 MB of L2 cache split across the two fabric and cache dies at an aggregate 54 TB/s.^[8][9]

Some coverage of the launch described the MI455X as 12 compute chiplets plus three 3 nm chiplets. AMD's own datasheet itemises 8 accelerated compute dies and 2 I/O dies, and die-level analysis of the package places the two fabric and cache dies between them, so the shipping layout is 8 + 2 + 2.^[8][9][34]

Compute and precision support

Peak throughput figures below are AMD's published specifications for the MI455X. All are vendor-reported and represent theoretical peaks, not measured performance.

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The new Matrix Cores in CDNA 5 add native support for the OCP MX microscaling FP4 and FP6 formats that are also used by Blackwell, alongside FP8, BF16, FP16, FP32, and FP64.

The most consequential design decision in the family is the collapse of double precision on the AI part. The MI355X delivers 78.6 TFLOPS of FP64; the MI455X delivers 5 TFLOPS, a reduction of roughly 94 percent. AMD spent that transistor budget on low-precision matrix throughput and HBM4 bandwidth instead. The MI430X exists precisely because that trade is unacceptable to scientific computing customers: it restores hardware FP64 at up to 288 TFLOPS.^[1][13]

HBM4 memory

Each MI455X carries 432 GB of HBM4 across 12 stacks of 36 GB, each on a 2,048-bit interface, for 23.3 TB/s of peak memory bandwidth. Against the MI355X (288 GB of HBM3e at 8 TB/s) that is 1.5 times the capacity and 2.9 times the bandwidth, and the 2.9x figure is the multiplier AMD itself cites for the generation.^{[1][8][10][11]}

The larger HBM4 footprint matters for very large mixture of experts models, which can hold more experts and KV cache per accelerator, and for agentic AI workloads that keep long context resident in memory. It is also AMD's clearest specification lead over Vera Rubin, whose first parts carry 288 GB.^[8]

The 19.6 versus 23.3 TB/s discrepancy

AMD's own published materials carry two different memory bandwidth figures for the same part, and both were still live in late July 2026.

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The 19.6 TB/s number dates to the June 2025 preview, when AMD had not finalized the HBM4 data rate. Every post-launch specification document and every independent teardown of the shipping part gives 23.3 TB/s.^{[8][9][10][11]} The arithmetic settles it: AMD claims 2.9 times the bandwidth of the MI355X, and 2.9 x 8 TB/s is 23.2 TB/s, not 19.6 TB/s.

The same split propagates to the rack level. A Helios rack of 72 MI455X GPUs at 23.3 TB/s each aggregates to roughly 1.67 to 1.7 PB/s, and those are the numbers AMD uses today: the MI400 series product page states 1.67 PB/s in its rack-performance text and 1.7 PB/s in its headline statistics, and the Helios launch blog states 1.7 PB/s. The older 1.4 PB/s figure, which is 72 times 19.6 TB/s, traces to AMD's October 2025 Helios blog written for the OCP Global Summit, before the specification was final, and it still circulates in analyst summaries derived from that material. No AMD document published at or after the July 2026 launch uses it. Treat 1.4 PB/s as the stale figure.^{[4][7][8][29]}

Interconnect

The MI400 series ships with two new interconnect technologies. For scale-up communication inside a Helios rack, MI400 accelerators support UALink alongside AMD's Infinity Fabric, making the family the first commercial silicon shipped with UALink support. AMD implements it as UALink over Ethernet (UALoE), giving 3.6 TB/s of bidirectional scale-up bandwidth per GPU and up to 260 TB/s aggregate across the 72 GPUs in a rack.^[8][9]

For scale-out communication between racks, AMD's specification page and datasheet both give each MI455X 600 GB/s of peak bidirectional scale-out bandwidth. In the fully populated Helios configuration that comes from three Pensando Vulcano 800 Gb/s AI NICs attached directly to the GPU, so 2,400 Gb/s in each direction, and it is what produces the rack-level figure of 43 TB/s (72 times 600 GB/s). AMD's specification page labels the link UALink while the datasheet describes rack-to-rack scale-out as Ethernet aligned with the Ultra Ethernet Consortium; the UALink hop is the private attachment between GPU and NIC, and the network proper begins at the Vulcano port. The host connection to the paired EPYC Venice CPU runs over 256 GB/s of bidirectional Infinity Fabric.^{[5][8][33][34]}

Product lineup

MI455X

The MI455X is the flagship of the family and the only variant qualified for the Helios rack-scale platform. AMD launched it on 2026-07-23 and expects Helios systems in customer hands in the second half of 2026. It targets hyperscale AI training clusters, the largest distributed inference deployments, and frontier model training runs.^[1][3]

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MI430X

The MI430X is the HPC and sovereign AI variant, announced alongside the MI455X on 2026-07-23 but expected to reach customers in 2027. It keeps the 432 GB HBM4 configuration and adds hardware double precision at up to 288 TFLOPS of FP64, roughly 58 times the MI455X figure and about 3.7 times the MI355X. AMD targets it at national laboratories, government cloud customers, and supercomputing centers, and has named the US Department of Energy and Oak Ridge Discovery system and the European Alice Recoque and Herder systems as expected MI430X deployments.^[1][13][32]

MI440X

The MI440X was disclosed at CES on 2026-01-06 as an enterprise part for standard 8-GPU on-premises servers paired with an EPYC Venice CPU. It was absent from AMD's Advancing AI 2026 launch release and from the MI400 series product page, and AMD has published no specification sheet for it. Some analyst summaries of the launch still list it as one of three family members. As of 2026-07-27 the correct description is disclosed but not launched.^[12][18]

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What is the AMD Helios rack-scale system?

Overview

Helios is AMD's first complete rack-scale AI system and the delivery vehicle for the MI455X. AMD describes it as a reference design rather than a single SKU, so OEM partners and ODMs sell their own Helios-compatible racks against the AMD specification. AMD's launch release names Bull, HPE, Lenovo and Supermicro as the OEMs, with Sanmina and Wiwynn as infrastructure partners. The system uses the Open Compute Project Open Rack Wide double-wide standard, which Meta originally contributed to OCP. See AMD Helios for the full system article.^[7][29][30]

A single rack integrates 72 MI455X accelerators and 18 EPYC Venice CPUs across 18 compute trays, each tray holding four GPUs and one CPU. Scale-out networking is carried by up to 216 Pensando Vulcano 800 Gb/s AI NICs: each tray takes two NIC boards populated with four or six Vulcano parts each, so a fully populated tray holds twelve and every GPU gets three. Scale-up switching is 12 Broadcom Tomahawk 6 ASICs spread across six switch trays, two per tray. Cooling is direct-to-chip liquid throughout.^[7][8][9]

Performance and specifications

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Power and thermals

AMD has published no TDP or board power figure for any MI400 part and no rack power figure for Helios, and the company's Helios launch blog treated power and thermal detail as material shared only under NDA with partners. Third-party reports of rack draw differ substantially, with one hands-on write-up citing 225 to 245 kW depending on workload; per-GPU figures circulating on aggregator sites in the 2,000 to 2,500 W range have no AMD source behind them and should not be treated as specifications.^[7][8][11]

AMD's rack-level performance claims

Both headline claims from the launch are AMD Performance Labs numbers tied to numbered endnotes, and both depend on the workload and operating point chosen.

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The qualifier matters. AMD's technical blog states the figure as "up to 34X ... at high interactivity," while the press release drops the interactivity condition and presents 34x as a flat generational improvement.^[1][2]

How does the MI400 compare to other accelerators?

Generational comparison

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The step from CDNA 4 to CDNA 5 is the largest AMD has taken in the Instinct line: capacity up 1.5 times, bandwidth up 2.9 times, dense 4-bit and 8-bit matrix throughput up about 4 times (AMD's own endnote MI400-006), and the scale-up fabric more than tripled. The MI355X numbers above are dense peaks; AMD also publishes structured-sparsity figures roughly twice as large for that part, and quoting those against the MI455X dense peaks understates the generational gain. The FP64 line runs the other way. Double precision on the AI part fell by more than an order of magnitude, and customers who need it are steered to the MI430X.^[1][8][13]

How does the MI400 differ from NVIDIA Vera Rubin?

The MI455X is positioned directly against NVIDIA's Vera Rubin platform, which pairs the Rubin GPU with NVIDIA's Vera CPU. Both vendors targeted second-half 2026 availability. The table below compares published vendor specifications; neither part has been independently benchmarked against the other.

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AMD leads on memory capacity per accelerator (1.5 times), aggregate rack memory, and per-GPU scale-out bandwidth. The two are close on bandwidth and peak 4-bit throughput. NVIDIA's advantage remains the maturity of the CUDA stack and a decade of deployed-at-scale operational experience, which no specification table captures.^[8][12]

Software

The MI400 series uses the AMD ROCm open-source software stack, AMD's counterpart to CUDA across compilers, libraries, runtimes, and AI frameworks. ROCm supports PyTorch, JAX, TensorFlow, vLLM, SGLang, and the Hugging Face Transformers library, with tuned container images for open models including Llama 4, DeepSeek, and Qwen.^[21]

At Advancing AI 2026 AMD introduced ROCm.ai, described as an AI-driven development platform intended to help coding agents such as Claude, Codex, and Cursor understand AMD platforms and ROCm APIs natively.^[1][2]

Public ROCm support lags the hardware announcement. The ROCm compatibility matrix published with release 7.14.0 and dated 2026-07-16 lists Instinct support only through gfx950 (MI355X, MI350X, MI350P), gfx942 (MI325X, MI300X, MI300A), gfx90a, and gfx908. No MI400-series part and no CDNA 5 gfx target appears in that matrix, and it had not been updated to add one as of 2026-07-27. That is normal for hardware whose first systems ship later in the year, but it means there is no publicly installable ROCm build that names the MI455X.^[21]

Independent benchmarking status

As of 2026-07-27 there was no independent benchmark result for any MI400-series part. AMD's most recent MLPerf submission was to MLPerf Inference v6.0, whose results were published on 2026-04-01 and which used MI355X systems; that round included a heterogeneous submission from Dell and MangoBoost spanning MI300X, MI325X and MI355X systems that reached 141,521 tokens per second on Llama 2 70B Server, while AMD's own multinode MI355X results crossed one million tokens per second on Llama 2 70B. No MI455X entry appeared in that round, and no later MLPerf round had published results at the time of writing.^[22][23]

Every performance number AMD has published for the MI400 series is therefore either a theoretical peak derived from clock and unit counts or an AMD Performance Labs measurement under an AMD-chosen configuration. Analyst coverage of the launch made the same point: as NAND Research put it, every headline benchmark comes from AMD's own labs, and ROCm's practical parity with CUDA remains unproven outside AMD's demonstrations.^[12]

Customers and deployments

Anthropic

On 2026-07-22, AMD and Anthropic announced a strategic partnership covering up to 2 gigawatts of MI450-series GPUs deployed in Helios rackscale solutions, with the first gigawatt beginning in the first half of 2027. AMD also disclosed an intended strategic equity investment in Anthropic of up to $5 billion. The investment is future-dated and tied to deployment progress rather than committed capital at announcement.^[15]

OpenAI

On 2025-10-06, AMD and OpenAI announced a multi-year partnership covering 6 gigawatts of AMD GPU capacity, beginning with a 1 gigawatt deployment of MI450-series GPUs. At the time it was the largest single non-NVIDIA AI customer commitment ever signed. AMD did not put a contract value on it; chief financial officer Jean Hu said only that the partnership was expected to deliver tens of billions of dollars in revenue for AMD. As part of the agreement AMD granted OpenAI a warrant to purchase up to 160 million shares of AMD common stock at a nominal exercise price, vesting against deployment milestones and AMD share-price targets; at full vesting the warrant represents roughly a 10 percent stake in AMD.^[16][26]

The schedule moved between announcement and launch. The original release described the first gigawatt arriving in the second half of 2026; AMD's Advancing AI 2026 release states that OpenAI expects to bring Helios online beginning in the fourth quarter of 2026, with deployments accelerating through 2027.^[1][16]

Oracle Cloud Infrastructure

Oracle and AMD expanded their partnership in October 2025 to include MI400-series deployments on Oracle Cloud Infrastructure, following Oracle's June 2025 announcement that OCI would offer zettascale AI clusters of up to 131,072 MI355X accelerators. AMD's MI455X materials cite Oracle Cloud Infrastructure as deploying 50,000 MI455X GPUs beginning in 2026. Oracle's AMD capacity is linked indirectly to OpenAI, which has separately contracted Oracle for compute that runs on a mix of NVIDIA and AMD silicon.^[5][25]

Other customers

AMD's Advancing AI 2026 release named Meta (validating 6th Gen EPYC and testing Helios racks), Microsoft, Oracle, HUMAIN, Tensorwave, Vultr, and Cirrascale among MI400-era partners, alongside collaborations with Cerebras, AT&T, and Cisco. Meta is a structurally important partner because the OCP Open Rack Wide standard Helios uses originated as a Meta contribution to OCP. Several national supercomputing centers in the United States and Europe have committed to MI430X procurements for post-exascale systems.^[1][7][32]

Manufacturing and supply

MI455X compute dies are manufactured on TSMC N2, making the part one of the first high-volume products on that node. The I/O dies and the fabric and cache dies use N3, and the package is assembled with TSMC CoWoS-L. HBM4 stacks come from SK hynix and Samsung. AMD has said Helios racks and MI400-series GPUs are on track for the second half of 2026. The tightest constraint on the ramp is HBM4 supply, since each MI455X consumes 12 stacks and early HBM4 output is shared across AMD, NVIDIA, and other accelerator vendors.^[8][20][27]

Reception and analysis

Reception of the launch focused on three things: the memory capacity lead over Vera Rubin, the Anthropic and OpenAI commitments as multi-year demand anchors independent of NVIDIA's customer base, and Helios itself, which moves AMD into competition with NVIDIA on integrated racks rather than loose accelerators. Analysts had flagged the shift to a 72-GPU UALink-over-Ethernet pod as the structurally important change well before launch.^[11][12][31]

The skepticism is consistent and specific. ROCm has no public MI400 support as of late July 2026. There are no independent benchmarks. AMD has not disclosed power or price, which makes the tokens-per-dollar claim impossible to check from outside. The 34x throughput figure holds only at one operating point on one model. And the family's headline part gives up nearly all of its double-precision capability, a trade that works for inference-heavy buyers and not at all for the HPC customers who now have to wait until 2027 for the MI430X.^[1][12][21]

See also

• AMD
• AMD Advancing AI 2026
• AMD Instinct MI455X
• AMD Instinct MI430X
• AMD Instinct MI355X
• AMD Instinct MI325X
• AMD Instinct MI300X
• AMD Helios
• AMD EPYC Venice
• NVIDIA Vera Rubin
• NVIDIA Blackwell
• HBM4
• ROCm
• UALink
• Ultra Ethernet
• MLPerf
• FP4
• GPU computing
• Anthropic
• OpenAI

References

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