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Taiwan Semiconductor Manufacturing Company (TSMC) is the world's largest dedicated independent semiconductor foundry, headquartered in the Hsinchu Science Park in Taiwan. Founded in 1987 by Morris Chang, the company invented the "pure-play foundry" business model: it manufactures chips designed by other companies and does not sell its own branded silicon. That single decision, more than any other, made the modern fabless industry possible. Without TSMC there would be no Nvidia data-center business, no Apple Silicon, and no realistic supply path for almost any leading-edge AI accelerator on the market today.
In 2025 TSMC reported NT$3,809 billion in net revenue, equivalent to about US$122 billion, a 35.9 percent rise in dollar terms over 2024, with high-performance computing (HPC) responsible for 58 percent of full-year revenue. The company employed roughly 90,557 people at the end of 2025 and held close to 70 percent of global foundry revenue, with an even larger share of leading-edge logic capacity below 7 nanometers. TSMC is now the indispensable manufacturing hub of the AI hardware industry, and the geopolitical contests around it reflect that.
Morris Chang founded TSMC in February 1987 with NT$5.5 billion (about US$220 million) of starting capital. Roughly half came from the Taiwanese government's National Development Fund, which took a 48 percent stake. Dutch electronics group Philips contributed technology and capital for just under 28 percent, and the rest came from local Taiwanese investors. Chang, who had spent a quarter century at Texas Instruments before being recruited to lead Taiwan's Industrial Technology Research Institute, was 56 when the company opened its doors.
The new firm did something nobody else was doing at scale: it built fabs but refused to design or sell its own chips. Every customer would be served on the same neutral footing, and TSMC would never compete with the people whose products it made. That promise is what eventually convinced fabless startups to trust an outside foundry with their intellectual property. Designers like Nvidia, AMD, Qualcomm, Broadcom, MediaTek, Marvell, and dozens of smaller AI accelerator startups would never have grown into multi-billion-dollar businesses if they had needed to build their own fabs.
Morris Chang served as TSMC's chief executive from 1987 to 2005 and as chairman until 2018. When he retired in June 2018 the company split his roles: Mark Liu became chairman and C.C. Wei became chief executive. Liu stepped down at the 2024 annual meeting, after which Wei took over as both chairman and CEO, the first executive to hold both titles since Chang. Chang himself remains an active public figure on Taiwan's chip strategy and a frequent commentator on US-Taiwan technology policy.
TSMC's product is wafers. A customer such as Nvidia, Apple, AMD, or Cerebras hands TSMC a finished design (a GDSII file plus all the metal and process options it has selected), and TSMC manufactures that design on the requested process node, dices the wafer, and ships either bare die or fully packaged parts back. Customers pay per wafer, with prices that scale steeply at the leading edge. By 2024 a single 300mm wafer at the 3 nm node reportedly cost north of US$20,000.
The company's revenue mix changed dramatically as AI demand exploded. In 2020, smartphone chips were 46 percent of TSMC revenue and HPC was 36 percent. By full-year 2025, smartphones had fallen to 29 percent and HPC, the segment that includes Nvidia's data-center GPUs, AMD's MI-series accelerators, and the various hyperscaler AI chips, had risen to 58 percent. In Q4 2025 specifically, HPC reached 55 percent of revenue and smartphones 32 percent. Apple, which spent roughly US$24 billion at TSMC in 2025, was still the largest single customer, but the cluster of AI buyers led by Nvidia is on track to overtake it.
TSMC's geographic revenue mix is also lopsided. North America accounted for about 75 percent of net revenue in 2025, mostly through US fabless designers shipping wafers back to be assembled into systems sold globally.
TSMC defines the leading edge of digital logic. Each new node delivers a step in transistor density, switching speed, and energy per operation, and the cadence has become roughly two years per major generation. The table below sketches the modern history, with first volume-production years and notable AI-relevant customers.
| Node | Volume year | Key feature | Notable AI / HPC chips |
|---|---|---|---|
| 28 nm | 2011 | Last planar HKMG node | Long-running mature node, still significant revenue |
| 16 nm / 12 nm | 2015 | First TSMC FinFET | NVIDIA Pascal P100, early Tesla AI chips |
| 10 nm | 2017 | Short-lived stepping | Apple A11 |
| 7 nm (N7) | 2018 | DUV only, no EUV | NVIDIA A100, AMD EPYC "Rome", Cerebras WSE-2, Tesla Dojo D1 |
| 7 nm+ (N7+) | 2019 | First TSMC EUV node | Huawei Kirin 990 5G, AMD chiplets |
| 5 nm (N5) | 2020 | Heavy EUV, ~13 EUV layers | Apple A14 / M1, AMD MI300 GPU chiplets |
| 4 nm (N4 / N4P) | 2022 | N5 family refinement | NVIDIA H100 (custom 4N), NVIDIA Blackwell B100/B200 (4NP), AMD Bergamo |
| 3 nm (N3 / N3E / N3P) | 2022 to 2024 | Last FinFET node | Apple A17 Pro / M3 / M4, Google TPU v6, Google Tensor G5 |
| 2 nm (N2) | 2025 (Q4) | First TSMC GAA nanosheet | Apple, AMD, Nvidia, MediaTek next-gen designs |
| A16 (1.6 nm class) | Planned 2H 2026 | GAA plus Super Power Rail backside power | High-end AI / HPC designs |
| A14 (1.4 nm class) | Planned 2027 to 2028 | Next-gen GAA | Not yet disclosed |
A few details deserve unpacking. N7 launched in April 2018 using only deep-ultraviolet (DUV) lithography; it was the node behind Nvidia's A100, the GPU that powered the first wave of large-language-model training. The N7+ refresh in 2019 was TSMC's first commercial use of extreme-ultraviolet (EUV) lithography from ASML, applied to four critical layers. N5, in volume from April 2020, was the first node where EUV did the heavy lifting, with roughly 11 to 13 EUV mask layers replacing about 35 immersion layers that earlier nodes would have needed.
The "4 nm" name is largely marketing. N4, N4P, and N4X are extensions of the N5 family with denser libraries and tweaked transistors rather than a wholly new generation. Nvidia's H100, the workhorse of the 2023 to 2025 AI training boom, runs on a TSMC-customized variant called "4N" (an Nvidia-specific subset of N4 with extra metal layers and yield tuning), with 80 billion transistors on an 814 mm² die. The Blackwell generation that followed, including B100, B200, and the GB200 superchip, was built on TSMC's 4NP process and ships with two reticle-limit dies stitched together by a 10 TB/s NV-HBI link, a packaging trick made possible by TSMC's CoWoS-L interposer technology. Nvidia's Hugo-class designs would have been simply impossible without these two TSMC services running in tandem: a leading-edge node and an interposer big enough to hold two giant dies plus stacks of HBM.
N3 entered volume production at the end of 2022 in Tainan's Fab 18. Apple bought essentially the entire first wave (Apple secured close to 100 percent of N3B early supply) for the A17 Pro in iPhone 15 Pro and the M3 family. The N3E refresh in 2024 widened the customer base, and Google's Tensor G5 mobile chip and the Google TPU v6 (Trillium) data-center chip both moved onto TSMC 3 nm.
N2 is the big architectural break. It is TSMC's first node to abandon FinFET in favor of gate-all-around (GAA) nanosheet transistors, in which the gate wraps around stacked horizontal silicon channels instead of standing as a fin between source and drain. TSMC has stated that, compared with N3E, N2 delivers about 10 to 15 percent better performance at the same power, or 25 to 30 percent lower power at the same performance, with about 15 percent higher transistor density on mixed designs. N2 entered volume production in Q4 2025. The follow-on A16 (a 1.6 nm-class node) is scheduled for second-half 2026 and will add Super Power Rail (SPR), TSMC's name for backside power delivery, in which power-distribution wires are routed under the transistor layer instead of competing for space above it.
The leading-edge node gets the headlines, but in the AI era the binding constraint has often been TSMC's advanced packaging capacity rather than its 5 nm or 4 nm wafer output. TSMC offers three main advanced-packaging families:
Chip-on-Wafer-on-Substrate (CoWoS) stacks one or more logic dies and several stacks of HBM (high-bandwidth memory) on top of a silicon interposer. CoWoS-S uses a passive silicon interposer and was sufficient through the H100 era. CoWoS-L, used for the Nvidia H100 successor Blackwell B200 and GB200, uses a more flexible reconstituted interposer with embedded local silicon bridges (LSI), allowing larger combined die areas. TSMC has been pushing CoWoS interposer dimensions toward 9.5 reticle-area equivalents by 2027.
Integrated Fan-Out (InFO) is a smaller, lower-cost packaging option used heavily for mobile SoCs, including most Apple A-series and M-series chips, where it provides a thinner package with shorter routing.
System on Integrated Chip (SoIC) stacks active logic die directly on top of other active die using bond pads at very fine pitches. AMD's 3D V-Cache CPUs and parts of the MI300 use SoIC to put cache or logic vertically on top of the compute layer.
For most of 2023 through 2025, the gating factor on Nvidia H100 and B200 supply was not the 4N wafer output, it was CoWoS interposer capacity. TSMC roughly doubled CoWoS capacity in 2024 and again in 2025, and capacity is reportedly still booked out years in advance. By 2026 Nvidia alone is estimated to be taking around 60 percent of TSMC's CoWoS output, leaving AMD, AWS, Google, and the AI startup ecosystem to fight over the rest. The "chip shortage" of the AI era is, more accurately, a packaging shortage.
The table below captures the chips at the heart of modern AI training and inference and the TSMC processes that make them.
| Customer | Chip | TSMC process | Packaging |
|---|---|---|---|
| Nvidia | A100 (Ampere) | N7 | CoWoS-S with HBM2e |
| Nvidia | H100 (Hopper) | Custom 4N | CoWoS-S with HBM3 |
| Nvidia | Blackwell B100, B200, GB200 | 4NP | CoWoS-L with HBM3e |
| AMD | Instinct MI250, MI300, MI325X | N5 logic plus N6 IO and cache chiplets | CoWoS plus 3D SoIC stacking |
| AMD | EPYC server CPUs (Genoa, Bergamo, Turin) | N5 / N4 / N3 chiplets | InFO_oS, organic substrate |
| Apple | A14 / M1 | N5 | InFO |
| Apple | A17 Pro / M3 / M4 family | N3B / N3E | InFO |
| TPU v4, v5e, v5p | TSMC 7nm and 5nm-class | CoWoS with HBM | |
| TPU v6 (Trillium) | N3 | CoWoS with HBM3 | |
| Tensor G5 (Pixel 10) | N3 | InFO | |
| AWS | Trainium 2 and Inferentia 2 (Annapurna designs) | N5 / N4 family | CoWoS |
| Cerebras | WSE-2 | N7 | Whole-wafer scale, no dicing |
| Cerebras | WSE-3 | N5 | Whole-wafer scale, 4 trillion transistors |
| Tesla | Dojo D1 training tile | N7 | InFO_SoW (system-on-wafer) |
| Various AI startups | SambaNova, Tenstorrent, Groq, Etched, Rebellions, MatX | N5 / N4 / N3 | CoWoS or InFO depending on design |
The Cerebras and Tesla wafer-scale parts are an unusual category. Cerebras WSE-3 fills an entire 300 mm wafer with around 900,000 cores and 4 trillion transistors, and TSMC manufactures the wafer without ever dicing it into individual chips. Tesla's Dojo D1 takes a different route: 25 D1 dies are mounted onto a fan-out wafer to form a single "training tile." Both are extreme expressions of how far TSMC's packaging stack can be pushed when a customer is willing to do something unusual.
TSMC's main fabs sit in Taiwan, but the company is now genuinely global, partly under commercial pressure from customers and partly under political pressure from Washington, Tokyo, Berlin, and Brussels. The big sites as of early 2026:
| Region | Site | Process nodes | Status |
|---|---|---|---|
| Taiwan | Hsinchu Science Park (Fab 12, etc.) | Mature plus advanced R&D | Operating, plus R&D for N2 and beyond |
| Taiwan | Taichung (Fab 15) | 28 nm to 16 nm class | Operating gigafab |
| Taiwan | Tainan (Fab 14, Fab 18) | N5, N3, N2 lead lines | Operating; Fab 18 is the N3 / N2 mother fab |
| Taiwan | Kaohsiung (Fab 22) | N2 and A16 | Ramping |
| United States | Arizona, Phoenix (Fab 21 Phase 1) | N4 | In production since late 2024 / early 2025 |
| United States | Arizona Phase 2 | N3 | Volume production targeted for 2H 2027 |
| United States | Arizona Phase 3 | N2 and A16 | Ground broken April 2025 |
| Japan | Kumamoto (JASM) | 28 / 22 / 16 / 12 nm | Phase 1 in production since late 2024 |
| Japan | Kumamoto Phase 2 | 6 / 7 nm class | Operation targeted by end of 2027 |
| Germany | Dresden (ESMC) | 28 / 22 nm and 16 / 12 nm FinFET | Construction; production targeted late 2027 |
| China | Nanjing | 16 nm and 28 nm | Operating; capped by US export controls |
The US expansion is the largest. In March 2025 TSMC announced it would lift its planned Arizona investment to US$165 billion, adding US$100 billion on top of the original US$65 billion plan. The full "gigafab cluster" will eventually contain six fabs, two advanced packaging facilities, and a research and development center. Phase 1 began producing N4 wafers in late 2024 and reached volume in 2025. Phase 2 will run N3, with volume production now targeted for the second half of 2027 (TSMC pulled this in from the original 2028 plan after pressure from US AI customers). Phase 3 will host N2 and A16 and broke ground in April 2025. Some 2025 reporting suggests the total Arizona commitment could climb further under tariff arrangements with the US administration.
The Japan venture, Japan Advanced Semiconductor Manufacturing (JASM), is jointly owned with Sony Semiconductor Solutions, Denso, and Toyota, with TSMC holding about 86.5 percent. JASM's first fab in Kumamoto opened in February 2024 and reached production with 12, 16, 22, and 28 nm processes the same year, mainly serving Sony's CMOS image-sensor business and Denso's automotive customers. A second fab is planned to start in 2027 and will add 6/7 nm-class capacity.
The Dresden fab, run as the European Semiconductor Manufacturing Company (ESMC), is 70 percent owned by TSMC with Bosch, Infineon, and NXP each holding 10 percent. Total investment is projected above 10 billion euros, with up to 5 billion euros from the German government under the European Chips Act. ESMC will run 28/22 nm planar and 16/12 nm FinFET processes, aimed largely at automotive and industrial customers. Construction broke ground in August 2024 and the structural build was complete by late 2025; production is targeted for late 2027.
Three technology stacks underpin TSMC's lead.
Lithography. TSMC was the first foundry to ramp EUV lithography (on N7+ in 2019) and is the largest single customer for ASML's EUV scanners. As of 2025 TSMC was the lead production user of ASML's High-NA EUV tools, which use a higher numerical aperture lens to print finer features in fewer mask layers. High-NA is a strategic gamble: at roughly US$380 million per machine and with very high facility requirements, it raises the cost of leading-edge nodes considerably, but it also widens the gap with competitors that cannot afford to deploy it at scale.
Transistor architecture. TSMC ran FinFET (a 3D transistor with a vertical fin channel) from the 16 nm node in 2015 through N3 in the early 2020s. N2 in 2025 marks the move to GAA nanosheet transistors, which give better electrostatic control and allow tighter pitches. The A16 node in 2026 will add backside power delivery (Super Power Rail), routing power wires under the transistor layer so that the upper metal stack can be devoted to signal routing. Intel has pursued a similar concept under the name PowerVia.
Packaging. CoWoS, InFO, and SoIC together form what TSMC calls 3DFabric. They are the reason a modern AI accelerator with hundreds of billions of transistors and 144 GB or more of HBM3e can exist as a single "chip" from the system designer's point of view. TSMC has roughly doubled CoWoS capacity year over year in 2024 and 2025 to keep up with AI demand and is still the bottleneck.
TSMC's centrality to global computing has turned the company into a strategic asset. By some estimates TSMC manufactures more than 90 percent of the world's leading-edge logic, and roughly 92 percent of the most advanced chips designed by US companies are fabricated by TSMC. That concentration produced the "silicon shield" idea, which is the argument that no major power can afford to risk a conflict that disrupts Taiwanese fabs, because the resulting hit to global computing would be intolerable for everyone, including China.
The shield is now being deliberately thinned. The US CHIPS and Science Act of 2022 provided about US$50 billion in subsidies for domestic chip manufacturing, with TSMC's Arizona project receiving multi-billion-dollar grants and loan guarantees. The flip side is that TSMC has agreed to restrict expansion of leading-edge capacity in China and to comply with US export controls. By 2024 and 2025, TSMC had stopped accepting new orders for advanced AI chips from designers it suspected might route product to Huawei or other restricted Chinese AI buyers, and the company has been phasing Chinese-made equipment out of its N2 lines. TSMC's Nanjing fab continues to run, but it is capped at 16/28 nm and is not part of the leading-edge AI supply.
A few features of how TSMC operates explain why competitors keep failing to catch up. The mother fab for each new node (Fab 12 for N7, Fab 18 for N5, N3, and N2) absorbs the worst of the early-yield problems, then knowledge is replicated to sister fabs, which is why each generation hits volume yield faster than the last. Customer designs are version-controlled, libraries are co-developed with EDA partners (Cadence, Synopsys), and reference flows are made available so a small fabless company can tape out on N3 with a fraction of the engineering staff that an integrated device manufacturer would need. Capital intensity is unusually disciplined: TSMC spent about US$40 billion in 2025 capex, has guided to US$52 to 56 billion in 2026, and funds new nodes from operating cash flow rather than debt. High gross margins (high-50s percent in 2025) and high capex create a self-reinforcing flywheel that raises the cost of competing. And the company has refused to compete with its customers. It has no Apple Silicon clone, no Nvidia GPU clone, no Cerebras alternative. That neutrality is the single most important asset TSMC owns, and Morris Chang's insistence on it from 1987 onward is the reason the company exists at all.
Samsung Foundry is the only other foundry currently producing leading-edge logic below 5 nm. Samsung adopted GAA nanosheets earlier than TSMC (at its 3 nm node in 2022) but its 3 nm yields lagged badly, with public reporting suggesting roughly 50 percent yields versus TSMC's roughly 90 percent at comparable points. Customers including Qualcomm and Google's mobile Tensor team have moved away as a result.
Intel Foundry Services (IFS) is Intel's attempt to compete in the external-foundry market on its own leading-edge processes (Intel 18A and Intel 14A). Intel has won some customer commitments and runs its own data-center CPUs on its fabs, but it does not yet have the volume of external AI customers that would support a TSMC-style flywheel.
GlobalFoundries exited the leading-edge race in 2018 when it abandoned 7 nm development and now focuses on specialty processes for RF, automotive, and industrial customers.
SMIC (Semiconductor Manufacturing International Corporation) is China's leading foundry. It has reached 7 nm-class production using DUV multi-patterning but cannot buy EUV tools from ASML under US-led export controls. SMIC manufactures Huawei's Ascend AI accelerators and is the closest thing China has to a leading-edge alternative to TSMC. United Microelectronics Corporation (UMC), a fellow Taiwanese foundry, is the second-largest pure-play in Taiwan but stopped pursuing leading-edge logic and now focuses on the 14 nm-and-above market.
It is hard to overstate how much modern AI runs on TSMC silicon. Almost every flagship AI chip in production in 2025 was made by TSMC: the H100 and Blackwell families that train and serve the largest language models, AMD's MI300 and MI325X used by Microsoft and Meta, the AWS Trainium and Inferentia chips inside Amazon Bedrock, Google's TPU v6 (Trillium), Apple's M-series Neural Engines, the entire Cerebras and Tesla Dojo programs, and a long tail of inference startups. The few exceptions, such as Huawei's Ascend on SMIC, prove the rule. When industry observers describe a "compute bottleneck" for training the next generation of frontier models, what they are most often describing is a TSMC bottleneck: not the wafer fab itself, but the CoWoS interposer line that turns those wafers into HBM-stacked accelerators.
As long as TSMC's leading edge is concentrated in Taiwan, the entire global AI build-out has a single point of physical risk. As that capacity migrates, slowly and expensively, to Arizona and Kumamoto and Dresden, the shape of the industry shifts with it. Whether Arizona's gigafab cluster can really replicate the speed of Taiwan, or whether Taiwan stays the irreplaceable center for another decade, is one of the few open questions whose answer will shape how the AI hardware era plays out.