Broadcom Tomahawk 6
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Last reviewed
May 31, 2026
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13 citations
Review status
Source-backed
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v1 · 1,993 words
Add missing citations, update stale details, or suggest a clearer explanation.
The Broadcom Tomahawk 6 is an Ethernet switch chip built for the networks that connect large clusters of AI accelerators. Broadcom announced it on June 3, 2025, and described it as the first switch to put 102.4 terabits per second of switching capacity into a single device, which the company said was double the bandwidth of any Ethernet switch then on the market. [1][2] The part belongs to Broadcom's long-running StrataXGS Tomahawk line, and it is aimed squarely at the bandwidth crunch created by training and serving large models across tens of thousands to more than a million chips. [1][3]
The short version is that AI training and inference move enormous amounts of data between accelerators, and the switch is the box that ties those accelerators together. Doubling how much a single switch can move changes the math for how a data center operator builds the fabric. With more capacity per chip you can connect more accelerators through fewer layers of switching, which lowers latency, cuts the number of optical transceivers and cables, and reduces power. The Tomahawk 6 is Broadcom's bid to make standard Ethernet the default fabric for that job, in direct competition with InfiniBand and with NVIDIA Spectrum-X.
Broadcom is the dominant merchant vendor of switch chips, meaning it designs the silicon and sells it to the companies that build switches and the hyperscalers that run them, rather than shipping finished switches under its own brand the way a systems vendor would. The Tomahawk family targets the high-bandwidth, fixed-configuration switches that fill cloud and AI data centers, and a sibling line called Jericho targets deeper-buffer routing roles. Around these switch chips Broadcom sells a wider kit for AI networks that includes Thor network interface cards, optical DSPs, retimers, and co-packaged optics, plus the software to drive them. [1][4]
The company sits among the largest semiconductor firms in the world. It crossed a one trillion dollar market value in December 2024, and reported fiscal 2025 revenue of about 63.9 billion dollars, with AI-related products a growing share of that total. [5] That scale matters here because building a 102.4 Tbps switch on a leading process node, with co-packaged optics and a full ecosystem of NICs and optics around it, is expensive, and Broadcom can spread that cost across the many switch makers and cloud operators that buy its silicon.
The headline number is 102.4 Tbps of switching capacity in one chip. [1] The previous generation, the Tomahawk 5, delivered 51.2 Tbps, so the Tomahawk 6 doubles per-chip throughput in a single step. [3][6] Press coverage and analysis reported the chip is built on a 3 nanometer process and uses a multi-die, chiplet-style design that separates the high-speed serializer and deserializer circuits from the main packet-processing die, which is part of how Broadcom fit so much bandwidth into one package. [6][7]
The practical payoff of more capacity per switch is a flatter network. AI clusters are usually wired as fat-tree or Clos fabrics built from tiers of switches, and each extra tier adds hops, latency, optics, and cost. When each switch can move twice as much traffic, an operator can collapse a tier. Broadcom said the Tomahawk 6 lets a scale-out network reach more than 100,000 accelerators using a two-tier topology where a previous generation would have needed three tiers. [1][7] Independent reporting put a concrete number on it, describing support for as many as 128,000 GPUs at 200G links in two tiers instead of three. [7] Fewer tiers means fewer switches, fewer transceivers, fewer cables, lower power, and lower tail latency, all of which matter when a single slow link can stall a synchronized training job.
That is the core reason switch bandwidth has become a bottleneck worth a flagship chip. As accelerator counts climb toward and past a million chips per site, the network rather than the individual processor often sets the ceiling on how fast a cluster trains, so doubling switch capacity translates fairly directly into either bigger clusters or cheaper ones at the same size. [1][3]
The Tomahawk 6 reaches its capacity through high-speed SerDes lanes, and Broadcom offers two main flavors. One configuration provides 1,024 lanes of 100G SerDes, which suits clusters that want long passive-copper reach and accelerators with native 100G interfaces. The other provides 512 lanes of 200G SerDes, Broadcom's leading-edge signaling rate, which the company said gives the longest reach over passive copper at that speed and the best power and cost profile. [1][8] These lanes can be grouped into ports at various speeds, so the same chip can present, for example, 512 ports of 200G, 1,024 ports of 100G, or 64 ports of 1.6 terabit Ethernet. [6][8] The two variants ship as the BCM78910 series, with model numbers reported as the BCM78910 for 100G operation and the BCM78914 for 200G operation. [6]
For links that need optics rather than copper, Broadcom offers a co-packaged optics version. Co-packaged optics, or CPO, places the optical engines on the same package as the switch die instead of in pluggable transceivers at the faceplate, which shortens the electrical path, cuts power, and removes a common source of link failures. [1][9] Broadcom branded the CPO variant the Tomahawk 6 Davisson and announced it on October 8, 2025, calling it the industry's first 102.4 Tbps switch with co-packaged optics and Broadcom's third generation of the technology after the earlier Tomahawk 5 Bailly part. [9][10] The Davisson integrates 16 optical engines running at 200G per channel, built with TSMC's compact universal photonic engine process, and Broadcom claimed roughly a 70 percent cut in optical interconnect power, more than 3.5 times lower than traditional pluggable optics. [9][10] The optical interfaces are specified to interoperate with standard 400G and 800G optics under IEEE 802.3. [9]
The Tomahawk 6 is compliant with the Ultra Ethernet Consortium specifications, the industry effort to adapt Ethernet for AI and high-performance computing with a better transport protocol, congestion handling, and loss avoidance that close much of the historical gap to InfiniBand. [1][2] On top of that the chip carries a feature set Broadcom calls Cognitive Routing 2.0, which adds adaptive load balancing across the whole fabric, congestion-aware flow control, fast failure detection, packet trimming, and fine-grained telemetry, all tuned for the bursty, synchronized traffic that comes from techniques like mixture-of-experts training and reinforcement learning. [1][8]
Broadcom also pushed the chip into scale-up networking, the tightly coupled domain inside a rack or a small group of racks where a handful of accelerators behave almost like one large processor. That role has traditionally belonged to proprietary links such as NVIDIA's NVLink. Broadcom argued that the same Ethernet silicon can serve scale-up too, connecting up to 512 accelerators in a single switched domain, which would let operators run one technology and one set of tools across both the scale-up and scale-out parts of a fabric. [1][7] The company paired this message with a separate, latency-optimized part called Tomahawk Ultra for the most demanding scale-up and HPC cases. [11]
For years InfiniBand, which NVIDIA owns through its Mellanox acquisition, was the default network for large GPU training because of its low latency and mature congestion control. The Tomahawk 6 is part of a broad industry effort to make Ethernet good enough to take that work, and the momentum has shifted. Market analysts at Dell'Oro reported that Ethernet had passed InfiniBand in AI back-end network share during 2025. [7]
NVIDIA's own answer on the Ethernet side is the Spectrum-X family, and the competition is close at the top. NVIDIA's Spectrum-X SN6810 reaches the same 102.4 Tbps class as the Tomahawk 6, while a larger SN6800 design is reported to push toward 409.6 Tbps across many 800G ports, and NVIDIA's Quantum-X line covers the InfiniBand side. [7] Timing has been a talking point: Broadcom shipped a 102.4 Tbps Ethernet switch in mid-2025, while some reports placed NVIDIA's matching 102.4 Tbps Spectrum-X generation in the second half of 2026. [7] The strategic contrast Broadcom emphasizes is openness. Its silicon goes into switches from many vendors and connects accelerators from many makers, which it frames as an alternative to buying networking, accelerators, and software as one tied stack. [7]
The Tomahawk 6 matters because it crossed the 100 Tbps line first and gave hyperscalers a standards-based way to build very large AI fabrics with fewer tiers. If Ethernet can match InfiniBand on performance for training, the economics and the multi-vendor supply chain favor it, and a chip like this is a large part of why that case now holds. [3][7]
The limits are worth stating plainly. Raw switch capacity is only one factor in how a real cluster performs, since the accelerators, their network interfaces, the optics, the cabling, and the collective-communication software all have to keep up, and a fabric is only as fast as its slowest contended link. The lead over competitors is also narrow and time-bound, because NVIDIA and others are shipping switches in the same capacity class. Co-packaged optics, the feature that most reduces power, is still early in real deployments, and reviewers have flagged concerns about serviceability and the larger blast radius when optics live inside the switch package rather than in field-replaceable modules, though Broadcom has said early field data shows the integrated lasers holding up. [7][10] And scale-up Ethernet faces competition not just from NVLink but from other consortium efforts, so its adoption in that role is not settled. [7]
| Attribute | Detail |
|---|---|
| Product | Broadcom Tomahawk 6 (StrataXGS, BCM78910 series) |
| Type | Ethernet switch chip for AI and cloud data centers |
| Vendor | Broadcom Inc. |
| Announced | June 3, 2025 (Davisson CPO variant October 8, 2025) |
| Switching capacity | 102.4 Tbps in a single chip |
| Prior generation | Tomahawk 5, 51.2 Tbps |
| Process node | 3 nm, multi-die chiplet design (per industry coverage) |
| SerDes options | 1,024 lanes of 100G, or 512 lanes of 200G PAM4 |
| Example port configs | 512 x 200G, 1,024 x 100G, or 64 x 1.6 terabit Ethernet |
| Co-packaged optics | Tomahawk 6 Davisson, 16 optical engines at 200G per channel, TSMC COUPE |
| CPO power claim | About 70% lower optical interconnect power, 3.5x vs pluggables |
| Standards | Ultra Ethernet Consortium compliant, IEEE 802.3 optics interop |
| AI features | Cognitive Routing 2.0, congestion-aware flow control, telemetry |
| Scale-up | Up to 512 accelerators in one switched domain |
| Scale-out | 100,000-plus accelerators in two tiers, targets 1M-plus XPU clusters |