Co-Packaged Optics

Co-packaged optics (CPO) is a hardware architecture that places active optical engines on the same first-level package substrate as a host application-specific integrated circuit (ASIC). The host may be a network switch, processor, or accelerator. High-speed data travels only a short distance electrically before the optical engine converts it to light for transmission over fiber. This package boundary separates CPO from conventional faceplate-pluggable transceivers and most on-board optical designs.^[1][2][4]

CPO is intended to reduce the electrical-channel loss, I/O power, and front-panel density pressure that accompany faster links in data centers, high-performance computing, and artificial intelligence clusters. Those benefits are design goals, not fixed properties. A CPO link still consumes power in its laser, modulator, receiver, control circuitry, forward error correction, and cooling, and some implementations retain a digital signal processor (DSP) in each optical engine.^[3][4][5]

Definition and package boundary

The Optical Internetworking Forum (OIF) defines CPO as active optical components attached to a common substrate containing the host ASIC. Its framework calls the ASIC, optical or electrical engines, and shared substrate a co-packaged assembly. An engine may be soldered to the substrate or use a socket, and the host ASIC may be a bare die or have its own local package within the larger assembly.^[4]

The definition does not require one photonic material or integration method. Silicon photonics is common because it can combine modulators, waveguides, photodetectors, and electronic interfaces at high density, but other laser and modulator technologies can feed a CPO engine. CPO also is not the same as optical circuit switching. Most CPO network products still use an electronic switch ASIC; the co-packaged photonics convert signals at the switch boundary rather than routing the payload through an all-optical switch.^[1][2]

Integration can occur at several physical levels. In a two-dimensional arrangement, the host and optical-engine dies sit side by side on a package substrate. A 2.5D design uses an interposer or redistribution layer for denser die-to-die wiring. Three-dimensional integration can stack photonic and electronic layers or place optical I/O beneath or above compute circuitry. The 2026 Nature Electronics review presents these as a technology roadmap, while also identifying thermal management, manufacturing, and standardization as unresolved constraints.^[1]

Architecture and signal path

A CPO link contains an electrical section, an electro-optical transmitter, an optical path, and an opto-electronic receiver. The partition between the host and the optical engine varies by design.^[2][4][5]

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The OIF framework describes four host-to-engine choices. A retimed engine contains clock recovery or DSP on both directions. A linear-amplified engine omits those digital functions and relies more heavily on the host SerDes to compensate for the complete electrical and optical path. A half-retimed design retimes only one direction. A direct-drive design reduces engine electronics further and requires a very short, tightly controlled host interface.^[4] CPO therefore does not mean "DSP-free," and two systems that share the CPO label can have different latency, power, and interoperability characteristics.

The OIF 3.2 Tb/s module agreement provides one concrete partition. It specifies 32 electrical lanes facing the switch ASIC, each operating at the CEI-112G-XSR rate, and line-side variants for eight 400GBASE-DR4 or eight 400GBASE-FR4 interfaces. The module includes DSP, driver, and transimpedance-amplifier functions and supports either an internal laser or light delivered from an external source. These values define that interoperable module, not a universal CPO size or lane arrangement.^[5]

Why optics move closer to the ASIC

At high signaling rates, a printed-circuit-board trace behaves as a frequency-dependent channel rather than an ideal wire. Conductor and dielectric loss, vias, sockets, connectors, impedance discontinuities, and crosstalk attenuate and distort the electrical waveform. Designers compensate with stronger drivers, equalization, retimers, or higher-quality board materials. Those measures consume power and board area, and their difficulty grows with lane rate and reach.^[1][3][4]

Pluggable transceivers sit at the faceplate, so their host electrical signals cross much of the board before conversion to light. CPO shortens that path to package scale. The optical fiber then carries the signal across the chassis, rack, or data hall with much lower distance-dependent loss than the corresponding high-speed copper channel. Moving conversion inward can also free faceplate area that would otherwise hold many individually caged modules and their heat sinks.^[3][4]

The expected gains depend on what is counted. A comparison can include only the host SerDes, the complete optical engine, the external laser, forward error correction, fans, liquid cooling, or the whole switch. Reach, modulation format, lane rate, fiber type, error-rate target, and redundancy also change the result. Academic reviews describe lower energy per bit and greater bandwidth density as the central opportunities, but they do not establish one CPO multiplier that applies to all systems.^[1][2][3]

Latency requires similar care. A shorter electrical path has less propagation delay, but that is only one part of a link. Removing a retimer or DSP can reduce processing delay; a retimed CPO engine still has that stage. Network topology, buffering, switching, protocol processing, and forward error correction often dominate end-to-end latency. CPO placement alone does not set an application's latency.^[4][5]

Laser placement and optical power

An optical engine needs a source of light. Designs generally place the laser within or next to the engine, or deliver continuous-wave light from an external laser source. Neither choice is part of the definition of CPO.^[2][4]

An integrated source has a short optical path to the modulator and avoids some connector, coupling, and splitter loss. It also places the laser in the thermal environment of a high-power host package and can make a failed source difficult to replace. External light moves the laser to another part of the chassis, often the faceplate. That isolates it thermally and lets an operator replace the source without disturbing the ASIC package, but the delivery path consumes optical power and adds fibers, connectors, splitting, monitoring, and laser-safety requirements.^[4][6]

OIF's External Laser Small Form Factor Pluggable agreement, ELSFP 2.0, specifies a faceplate-pluggable laser module for optical engines that lack integrated lasers. It includes a blind-mate electro-optical connector, cage, thermal interface, keying, power classes, and a mating sequence designed to prevent powered connection or disconnection. A separate ELSFP CMIS agreement defines management behavior. ELSFP standardizes a replaceable light-source interface; it does not dictate the complete optical engine or every wavelength and noise requirement of the link it powers.^[6][7]

External lasers can also support redundancy. One source may feed several engines, several sources may share an engine, or spare laser paths may remain available after a failure. Redundant sources and spare paths trade additional couplers and optical loss for less disruption after one laser fails. By contrast, one source feeding several engines makes that source a shared dependency, so the failure domain must be evaluated at system level.^[4]

Fiber attachment

A CPO assembly can aggregate a high lane count across several engines, and each engine must attach its assigned optical lanes to fiber without blocking cooling hardware or damaging the optical budget. A pigtailed engine bonds a fiber ribbon or bundle directly to the engine and routes it toward the front panel. A connectorized engine adds a detachable optical interface near the package. A mid-board connection can standardize pigtail length, reduce handling damage, and permit some rework, but every connection adds insertion and return loss.^[2][4][5]

Single-mode designs may use parallel fibers, multiple wavelengths on each fiber, or both. Multimode designs can use vertical-cavity surface-emitting lasers for shorter links. The chosen coupling scheme may approach the photonic die at an edge or from above. Fiber pitch, ferrule alignment, polarization, bend radius, adhesive stability, cleanliness, and connector mating life all affect yield and field procedure.^[2][4]

This makes fiber attach part of the package architecture rather than a final cabling step. An accessible front-panel connector can be inspected and remated; an internal connector may remain inaccessible until system test. A connector that is acceptable for a small pluggable module may not have the density, loss distribution, or manufacturing insertion life needed for a package serving many ports.^[4][11]

Standards and interoperability

CPO crosses package, electrical, optical, mechanical, thermal, control, and service boundaries. No single standard covers all of them. OIF classifies framework documents as informative and distinguishes them from its normative Implementation Agreements.^[4][8]

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The 3.2T OIF agreement reuses IEEE Ethernet optical specifications for DR4 and FR4 variants and uses CMIS for management. Reuse lets a co-packaged engine operate with installed cabling and line-side equipment when its optical budget meets the same interface. Interoperability at the fiber does not guarantee interchangeability at the package: the engine footprint, host electrical channel, cooling contact, fiber exit, and management implementation also have to agree.^[5][8]

The Open Compute Project's April 2024 short-reach photonics white paper recorded that CPO and linear pluggable optics had not reached commercial volume at that time. Its later AI-cluster program treated CPO, near-package optics, and linear optics as parallel work areas rather than a single predetermined transition.^[9][10] These materials document operator and ecosystem requirements, but product availability needs separate evidence.

The Optical Compute Interconnect MSA released its first line-interface specification in March 2026. Its 200G physical-medium interface uses four wavelengths at 53.125 Gbaud with non-return-to-zero signaling to carry a 212.5 Gb/s coded stream, and its roadmap permits pluggable, on-board, or CPO physical implementations.^[15][16] This is relevant to compute scale-up links, but it does not make those package forms mechanically interchangeable.

Comparison with neighboring approaches

The terms describe different aspects of a link and are not always mutually exclusive.^{[3][4][17][18]}

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LPO is primarily an electrical and signal-processing arrangement, not a package location. The OIF CPO framework itself includes linear, half-retimed, and direct-drive interfaces, while a faceplate module can be fully retimed. A CPO optical engine can therefore use linear signaling, and an LPO module remains physically pluggable.^[4][17]

NPO has a less consistent boundary. Some sources use it for board-mounted engines placed close to an ASIC but outside the first-level package. The OIF framework illustrates a socketed ASIC and engines on a common substrate and calls that arrangement NPO. Product comparisons should describe the actual substrate and socket arrangement instead of inferring it from the label alone.^[4][18]

Thermal design, manufacturing, and test

The optical engines sit next to a host ASIC that may dissipate hundreds of watts. Heat spreaders, cold plates, retention hardware, and fiber exits compete for space. Lasers and wavelength-sensitive photonic components can have different temperature limits from the electronic die, so designers may isolate the optical engine, stabilize selected devices, or move the laser to the faceplate. Liquid cooling can remove more heat, but it adds its own mechanical, contamination, and service requirements.^[2][4][6]

Manufacturing combines electronic integrated circuits, photonic integrated circuits, package substrates, electrical attach, optical coupling, fibers, and cooling hardware. Testing only the finished assembly makes a late defect expensive because a failed component can discard or require rework of the larger package. Production flows therefore need component screening and traceability across wafer, die, optical-engine, package, and system test.^[2][4][11]

Semiconductor Engineering reported in August 2026 that CPO test programs still varied in optical access, connector types, alignment, laser delivery, calibration, result formats, and component identifiers. Electrical test formats do not naturally carry wavelength sweeps, polarization-dependent loss, and other optical measurements. Without consistent unit genealogy, a system integrator cannot easily connect a final optical failure to a photonic-die lot, electronic-die lot, bond process, or test site.^[11]

Standard electrical and line-side optical interfaces therefore solve only part of the manufacturing problem. Automated test also needs repeatable optical access, connectors that survive many factory insertions, reference conditions, calibration practice, and data schemas. These remain areas of active industry work rather than settled properties of CPO.^[8][11]

Reliability and serviceability

A faceplate pluggable normally represents one replaceable port or a small group of lanes. A CPO engine can serve much more bandwidth inside a package, so its failure can affect more links and expose an expensive host ASIC to replacement risk. OIF's framework describes co-packaged engines as inherently less field-serviceable than faceplate pluggables and calls for component screening, monitoring, redundancy, and repairability at system level.^[4]

Mitigations include external replaceable lasers, socketed engines, redundant optical paths, lane sparing, and operation at reduced capacity after a fault. None makes every CPO design hot-swappable. A socket improves rework but consumes package area and adds a mechanical and electrical interface. A soldered engine offers higher density but makes replacement harder. A remote laser removes one common failure from the package while adding an optical delivery path.^[4][6]

Reliability comparisons must use the same failure boundary. A vendor may count fewer active components in one switch, while an operator may care about link availability, replaceable-unit failure, scheduled maintenance, and the number of ports lost per event. Early accelerated tests and vendor projections do not substitute for field data over a full service life.^[2][4]

Commercial systems and roadmap

Research prototypes and on-board optical systems preceded the current CPO product cycle, but a demonstration does not establish manufacturing scale. Broadcom announced its 51.2 Tb/s Tomahawk 5 Bailly CPO platform on March 14, 2024. It placed eight 6.4 Tb/s silicon-photonics engines around the switch ASIC. Broadcom said it had delivered Bailly to customers and would showcase the system at OFC 2024; the announcement did not quantify shipments.^[13]

By July 2026, TrendForce reported limited Bailly shipments, volume-manufacturing work with Delta Electronics and Micas Networks, and deployment validation with Meta. The same report said optical-engine yield, silicon-photonics supply, and advanced-packaging capacity were limiting expansion.^[12] "Limited shipments" and "deployment validation" do not establish a fleet-wide deployment count or open retail availability.

NVIDIA said on May 31, 2026 that NVIDIA Spectrum-X Photonics was in production. TrendForce later reported shipments to selected partners and expected capacity to expand during the second half of the year.^[12][14] The narrower independent description is evidence of an early commercial ramp, not proof that CPO had replaced pluggable optics across AI networks.

These switch products still connect to endpoints that may use pluggable transceivers, copper, or other optical forms. CPO at one side of a fabric does not make the complete cluster co-packaged. Compute-side optical I/O and common scale-up interfaces remain active development areas, as shown by the 2026 OCI specification and OCP work.^[10][15]

As of Aug. 20, 2026, public evidence supports a transition from prototypes and sampling to early manufacturing and selected-partner shipments. It does not support a claim of uniform, multi-vendor, high-volume deployment. Suppliers and analysts also use "production," "shipment," "validation," and "deployment" differently, so each status needs its own attribution and date.^[11][12][14]

Evidence limits

The Aug. 19, 2026 Nature Electronics article that prompted renewed attention to CPO is a review and roadmap, not a report of one newly demonstrated system. Its abstract surveys electrical subsystems, conversion interfaces, optical networks, and 2D through 3D integration, then identifies thermal management, manufacturing, and standardization as barriers. Nature's disclosure states that coauthor Seunghoon Hong is an SK hynix employee; the other authors declared no competing interests.^[1]

SK hynix's newsroom summary attaches numeric bandwidth, energy, and latency targets to that roadmap.^[19] Those values should be treated as targets attributed to the company and authors, not as universal measurements. The accessible Nature abstract does not show the configurations or calculations behind them, and the full paper was paywalled at publication.

The same caution applies to product comparisons. Power per bit depends on the accounting boundary, latency depends on more than package placement, and reliability depends on the replaceable unit and failure domain. CPO can shorten an electrical link, but whether it lowers the cost or energy of a deployed system must be measured for the specific engine, switch, cooling system, cables, topology, and workload.^[1][3][4]

See also

• NVIDIA Quantum-X Photonics
• NVIDIA Spectrum-X

References

1. ^Kim, Byungsoo, et al. "Co-packaged optics for high-performance computing and artificial intelligence." Nature Electronics 9, 853-867. Aug. 19, 2026. nature.com/...s41928-026-01681-6
2. ^Tan, Minghao, et al. "Co-packaged optics (CPO): status, challenges, and solutions." Frontiers of Optoelectronics 16, 1. 2023. pmc.ncbi.nlm.nih.gov/...PMC10027985
3. ^Minkenberg, Cyriel, et al. "Co-packaged datacenter optics: Opportunities and challenges." IET Optoelectronics 15. 2021. ietresearch.onlinelibrary.wiley.com/...ote2.12020
4. ^Optical Internetworking Forum. "Co-Packaging Framework Document," OIF-Co-Packaging-FD-01.0. Feb. 3, 2022. oiforum.com/...OIF-Co-Packaging-FD-01.0.pdf
5. ^Optical Internetworking Forum. "Implementation Agreement for a 3.2Tb/s Co-Packaged (CPO) Module," OIF-Co-Packaging-3.2T-Module-01.0. March 29, 2023. oiforum.com/...OIF-Co-Packaging-3.2T-Module-01.0.pdf
6. ^Optical Internetworking Forum. "External Laser Small Form Factor Pluggable (ELSFP) Implementation Agreement," OIF-ELSFP-02.0. January 2025. oiforum.com/...OIF-ELSFP-02.0.pdf
7. ^Optical Internetworking Forum. "Implementation Agreement for ELSFP CMIS," OIF-ELSFP-CMIS-01.0. September 2024. oiforum.com/...OIF-ELSFP-CMIS-01.0.pdf
8. ^Optical Internetworking Forum. "Implementation Agreements." Accessed Aug. 20, 2026. oiforum.com/...implementation-agreements-ias
9. ^Open Compute Project. "OCP White Paper on Short Reach, In Server Photonic Interconnects." Release 01, April 2024. opencompute.org/...el-bortz-dec-27-2023-r1d4-pdf-1
10. ^Open Compute Project. "The OCP Community Solving Difficult Problems in Deployment of Sustainable Large Scale AI Clusters." March 17, 2025. opencompute.org/...ainable-large-scale-ai-clusters
11. ^Meixner, Anne. "CPO Test Won't Scale Without Standardization." Semiconductor Engineering. Aug. 11, 2026, updated Aug. 12, 2026. semiengineering.com/...ale-without-standardization
12. ^TrendForce. "NVIDIA and Broadcom Begin Volume Ramp of CPO Switches, with Optical Engine Yield and Advanced Packaging Capacity Emerging as Key Expansion Bottlenecks." July 27, 2026. trendforce.com/...20260727-13151
13. ^Broadcom. "Broadcom Delivers Industry's First 51.2-Tbps Co-Packaged Optics Ethernet Switch Platform for Scalable AI Systems." March 14, 2024. broadcom.com/...61946
14. ^NVIDIA. "NVIDIA Vera Rubin Ramps Into Full Production to Power Agentic AI Factories Worldwide." May 31, 2026. investor.nvidia.com/...default
15. ^Optical Compute Interconnect MSA. "200G Optical Compute Interconnect Line Interface Specification," version 1.0. March 11, 2026. oci-msa.org/...-Optical-Phy-Specification-v1.0.pdf
16. ^Optical Compute Interconnect MSA. "Optical Scale-up Consortium Established to Create an Open Specification for AI Infrastructure Led by Founding Members AMD, Broadcom, Meta, Microsoft, NVIDIA and OpenAI." March 12, 2026. broadcom.com/...pecification-for-ai-infrastructure
17. ^Linear Pluggable Optics MSA. "Frequently Asked Questions." Accessed Aug. 20, 2026. lpo-msa.org/...faqs
18. ^Ericsson. "Co-packaged optics opportunities in radio-access networks." Ericsson Technology Review, 2023. ericsson.com/...co-packaged-optics-in-6g-ran
19. ^SK hynix Newsroom. "SK hynix's technology roadmap for co-packaged optics features in 'Nature Electronics,' as AI competition shifts from chips to systems." Aug. 20, 2026. news.skhynix.com/...cpo-in-nature-electronics