Dynamic random-access memory (DRAM) is the working memory of nearly every computer built since the late 1970s, and the physical substrate on which modern AI hardware runs. Each bit is stored as a small electric charge on a capacitor, guarded by a single access transistor. That one-transistor, one-capacitor (1T1C) arrangement was invented in 1967 by Robert Dennard at IBM, and it has survived essentially unchanged for close to five decades [1]. Everything characteristic about DRAM follows from it: the charge leaks, so DRAM is volatile and must be refreshed continuously; reading a cell drains it, so every read is destructive and has to be restored; and the charge is so small that a dedicated amplifier is needed to tell a one from a zero at all.

For an encyclopedia of artificial intelligence, DRAM matters because AI memory is made of it. High Bandwidth Memory is DRAM: an HBM stack is a set of DRAM core dies bonded over a base die and wired together with through-silicon vias, built from the same 1T1C cells, the same high-aspect-ratio capacitors and the same sense amplifiers as a commodity server module [1]. The reason HBM exists at all is that DRAM bandwidth has not kept pace with arithmetic throughput. Peak server hardware FLOPS grew about 3.0 times every two years over the period studied by Gholami and colleagues, while DRAM bandwidth grew only about 1.6 times and interconnect bandwidth about 1.4 times over the same interval [5]. Most large language model inference is therefore bound by how fast bytes can be pulled out of DRAM, not by how fast the accelerator can multiply them.

The one-transistor, one-capacitor cell

A DRAM array is a grid. Wordlines run along the rows and control the gate of the access transistor in every cell on that row. Bitlines run along the columns and connect to the source of each access transistor. Raising a wordline turns on every access transistor in the row at once, connecting each storage capacitor to its bitline; the intersection of the active wordline and a selected bitline identifies a single cell [1].

The charge involved is tiny. A modern storage capacitor holds roughly 6 to 7 femtofarads and stores on the order of 40,000 electrons when freshly written [1]. When the wordline opens, that charge is shared with the whole bitline, whose own capacitance may exceed 30 femtofarads, so the signal arriving at the end of the column is diluted by a factor of around five before anything has read it [1].

Recovering a usable logic level from that is the job of the sense amplifier, the second invention DRAM depends on. The first modern sense amplifier was developed by Karl Stein at Siemens in 1971, and it was independently rediscovered at Mostek, whose 16 kbit part combining 1T1C cells with sense amplifiers became the market leader by 1977 and fixed the architecture the industry still uses [1]. The circuit works differentially: the active bitline is compared against an idle neighbour held at a similar voltage, and the amplifier drives the small difference between them to a full rail. Because the cell is still connected to the bitline while this happens, the amplified value is written straight back into the capacitor. The read and the restore are the same operation [1].

The row of sense amplifiers attached to an open row is called the row buffer. Because a bank has exactly one row buffer, only one row per bank can be open at a time, and switching rows means closing the current one (precharge) before activating the next [4]. This is the origin of DRAM's page-locality behaviour: a hit in an already-open row is fast, a miss in a different row of the same bank is expensive, and the whole memory controller design problem is about scheduling around that asymmetry.

Volatility and refresh

The capacitor leaks. Junction leakage and subthreshold conduction through the access transistor drain the stored charge over milliseconds, so the contents must be read out and rewritten on a fixed schedule or the data is lost. The DDR3 standard specifies a 64 ms retention window, and a memory controller meets it by issuing 8,192 refresh commands across that window, one every 7.8 microseconds, so that every row is refreshed exactly once per interval [4]. SemiAnalysis reported in 2024 that some parts refresh as often as every 32 ms [1]. Refresh is not free: it happens entirely inside the chip with no data crossing the pins, which limits the energy cost, but it can still account for more than 10% of total DRAM power draw [1].

Volatility is the sharpest line between DRAM and NAND flash, which stores charge on a floating gate or in a charge-trap layer that holds its value with the power off. The two technologies have different cells, different economics and largely different manufacturers, and NAND occupies the tier below DRAM in the memory hierarchy rather than competing with it. SRAM, the tier above, holds each bit in a six-transistor latch that never needs refreshing but occupies roughly 120 F squared per bit against a DRAM cell's 6 F squared, which is about twenty times less dense and, per SemiAnalysis, more than a hundred times more expensive per byte [1].

Disturbance and row hammer

Repeatedly toggling a wordline stresses the coupling between neighbouring cells and accelerates charge leakage in adjacent rows. Kim and colleagues demonstrated this experimentally at ISCA 2014, showing that as few as 139,000 reads to a single DRAM row could flip bits in a nearby row, that disturbable cells existed in 110 of 129 commodity modules they tested, and that in the worst modules up to one cell in 1,700 was disturbable [4]. The effect, universally known as row hammer, is a direct consequence of scaling: the smaller and closer the cells, the weaker the stored charge and the stronger the coupling. Mitigations have since been written into the standards, including target row refresh, DDR5's Refresh Management, and the Directed Refresh Management added in HBM4.

Array organisation, timing, and the latency that never improved

A DRAM device is divided into banks, each bank into rows and columns, each bank with its own row buffer, and (from DDR4 onward) banks are further grouped into bank groups that can be interleaved to hide internal delays [10]. A representative 512 Mbit chip has four banks, each an array of 8,192 rows of 16,384 bits [6].

Reading an address means activating a row, selecting a column out of it, and eventually closing the row again. Each step has its own timing constraint:

Parameter	Name	What it measures
tRCD	RAS to CAS delay	Activating a row and getting it into the row buffer
tCAS (CL)	Column access strobe latency	Selecting a column out of the open row and putting it on the pins
tRP	Row precharge time	Closing the open row before another row in the same bank can be activated
tRC	Row cycle time	Activate to activate in the same bank, typically around 50 ns [4]

The headline number quoted for a memory module, such as 40-40-40, is tCAS-tRCD-tRP in clock cycles. Because those are cycles rather than seconds, and because the clock has been getting faster for twenty-five years while the array underneath has not, the cycle counts have inflated steadily while the actual elapsed time has barely moved.

The arithmetic is stark. A CAS latency of 10 to 15 nanoseconds corresponds to CL2 or CL3 on the 200 MHz clock of DDR-400, to CL4 through CL6 on DDR2-800, and to CL8 through CL12 on DDR3-1600 [6]. DDR2 modules spanned roughly 9.4 to 20 ns depending on grade [8]; DDR3 sat around 10 to 15 ns [9]; DDR4 modules ran timings from 10-10-10 at DDR4-1600 to 24-24-24 at DDR4-3200, which works out to between 12.5 and 15 ns [10]. In other words, the time to get the first word out of a closed DRAM row is about what it was in 2000.

Bandwidth over the same period went up by more than an order of magnitude. DDR-400 moved 400 million transfers per second, which on a 64-bit channel is 3.2 GB/s. DDR5 is standardised from 4000 to 8400 MT/s [11], so a single DDR5-6400 channel delivers 51.2 GB/s, and an HBM4 stack at the JEDEC base rate reaches 2 TB/s. The industry has been able to buy throughput by widening buses, raising signalling rates, adding banks and prefetching more bits per internal access, but none of that touches the sequence of physical events (charge sharing onto a bitline, amplification, restore) that sets the latency floor. The practical result for AI serving is that latency-sensitive, pointer-chasing workloads see almost no benefit from new DRAM generations, while streaming workloads such as reading model weights or a KV cache see most of it.

Why DRAM scaling stalled

DRAM used to scale faster than logic. Bit density per chip doubled roughly every 18 months at the peak, which is a hundredfold gain per decade. Over the decade to 2024, density improved by about 2 times in total, roughly an order of magnitude slower than the historic rate [1]. Three physical problems account for most of the slowdown.

The capacitor. DRAM uses a stacked capacitor sitting above a recessed-channel access transistor, formed as a narrow vertical cylinder lined with a metal-insulator-metal stack, historically a zirconium-oxide-based high-k dielectric [2]. Shrinking the cell shrinks the cylinder's diameter, which reduces its surface area and therefore its capacitance, so makers have compensated by making it taller. Modern capacitors are around 1,000 nm tall but only tens of nm across, and aspect ratios are approaching 100 to 1 [1]. Etching a straight hole at that aspect ratio without bowing, twisting or stopping early is at the edge of what plasma etch can do, and it must then be lined with several defect-free layers a few nanometres thick, uniformly, all the way down [1]. Micron's own description of its most recent node lists "advanced high aspect ratio etch processes" as one of the three enabling technologies alongside EUV and high-k metal gate CMOS [17]. Samsung's answer at the 20 nm generation was a honeycomb capacitor layout that staggered the cylinders rather than placing them on a square grid, buying about 21% more cell capacitance for the same dielectric [2].

Even with those tricks, capacitance keeps falling. TechInsights measured cell capacitance already below 10 fF at the D1z and D1a generations, and projects 5 to 6 fF at D1c against a manufacturer preference for staying above 6 to 7 fF; holding the line requires ultra-thin dielectrics with a dielectric constant above 50, with strontium titanate paired with ruthenium electrodes as the leading candidate [3].

The sense amplifier. Sense amplifiers are squeezed from both sides at once. Their pitch has to shrink to match the bitline pitch, which makes them less sensitive and more prone to variation and leakage; meanwhile the signal they have to resolve is getting smaller because the cells hold less charge [1]. Debra Bell, senior director of DRAM product engineering at Micron, described the second half of the problem as a timing and geometry trade: "It's a combination of your timing specs, how much time you have to move the charge onto the digit line, and then how long can you make the digit lines" [2]. Sensing margin, once an afterthought, is now among the hardest parts of a DRAM design.

The cell layout. DRAM has used a 6F squared cell since 2007, having moved there from 8F squared [1]. The theoretical floor for a single-bit cell is 4F squared, because a line-and-space pattern has a pitch of 2F in each direction, so once a maker reaches 4F squared the only remaining lever is shrinking F itself. TechInsights' shrink-factor data shows how hard that has become: Micron held a design-rule shrink factor of 0.75 to 0.85 for years, then slipped to 0.92 at D1z, and TechInsights expects shrink factors above 0.9 to persist across D1a, D1b and D1c, concluding that 10 nm is likely to be the last node for a 6F squared cell [3]. Adding EUV lithography did not change the trajectory much: SemiAnalysis noted that its introduction at Samsung's 1z and SK hynix's 1a nodes did not significantly increase density [1].

What the node names actually mean

DRAM node names are not feature sizes and have not been for a decade. The convention originally had a physical basis: nodes were designated by the half-pitch of the active area of the memory cell, and when the industry entered the "1x" regime around 2016 the labels mapped to real ranges, with 1x defined as roughly 17 to 19 nm, 1y as 14 to 16 nm, and 1z as 11 to 13 nm [2]. That mapping then broke. As Semiconductor Engineering reported in 2019, "some vendors have relaxed the scaling specs, creating some confusion in the market. Some DRAMs fall within these specs, while others don't", and the analyst Handel Jones of IBS summarised the resulting claims at 1z bluntly: "There is a lot of marketing going on right now" [2].

The Greek-letter generations that followed (1-alpha, 1-beta, 1-gamma, and in some vendors' notation 1a, 1b, 1c) carry even less physical information. They are sequence markers, not dimensions. Micron's public materials for 1-gamma describe it only as a "sixth-generation 10 nm class" node and quote relative improvements against the previous generation: more than 30% more bits per wafer, more than 15% higher speed, and more than 20% lower power, supporting DDR5 up to 9200 MT/s [17][18]. No nanometre figure appears anywhere in Micron's own description of the node [18]. The same is true of Samsung's and SK hynix's equivalents.

What is actually known about the physical dimensions comes from teardown analysis rather than from the manufacturers. TechInsights measures cell pitch (active, wordline and bitline), cell area and design rule directly from delayered parts, and publishes shrink factors between generations from those measurements [3]. Any nanometre figure attached to a DRAM node should be treated as a third-party characterisation and attributed to whoever measured it and when, not as a vendor specification. Comparing two makers' "1-beta" parts as though the label denoted the same geometry is a category error.

Standards and product families

The DRAM interface is standardised by JEDEC, the industry body whose committees are staffed by the memory makers, the controller vendors and the platform companies together. A JEDEC standard defines the pin interface, the command set, the timing parameters and the speed bins, but not the cell, the capacitor or the process; those remain each manufacturer's own. This division is why a DDR5 module from any of the three suppliers is interchangeable while the silicon inside is not.

The main memory line

Generation	JEDEC standard	Published	Data rates	Supply voltage	Prefetch
SDR SDRAM	JEDEC SDRAM specifications	1990s	66-133 MHz clock	3.3 V	1n [6]
DDR	JESD79	June 2000 [7]	200-400 MT/s	2.5-2.6 V	2n [7]
DDR2	JESD79-2	September 2003 [8]	400-1066 MT/s	1.8 V	4n [8]
DDR3	JESD79-3	2007 [9]	800-2133 MT/s	1.5 V (1.35 V DDR3L)	8n [9]
DDR4	JESD79-4	September 2012 [10]	1600-3200 MT/s	1.2 V	8n [10]
DDR5	JESD79-5	14 July 2020 [11]	4000-8400 MT/s	1.1 V	16n [7]
DDR6	not yet published	see below	reported 8800-17,600 MT/s [15]	not final	not final

DDR5 is the current server and client standard and made two structural changes worth naming. It splits each module into two independent subchannels with their own command and address buses [11], which raises the number of concurrent memory transactions a controller can keep in flight; and it makes on-die ECC mandatory, so every DDR5 die corrects errors internally before data leaves the chip [11]. The second change is a scaling concession as much as a reliability feature: cells small enough to be worth building are no longer reliable enough to ship uncorrected.

DDR6 status. As of August 2026 no DDR6 standard has been published and no DDR6 product has shipped. TrendForce reported in July 2025, citing Commercial Times and The Guru, that the main DDR6 draft was completed in late 2024, that Samsung, Micron and SK hynix had finished prototype chip designs and were doing interface testing with Intel and AMD, and that mass adoption was expected around 2027, with a reported speed range of 8,800 to 17,600 MT/s and a shift to four 24-bit subchannels [15]. SK hynix's own roadmap, presented at its SK AI Summit in November 2025, is considerably less aggressive: it places DDR6 in 2029 or 2030 and expects DDR5 to keep evolving in the meantime through higher-bandwidth module formats such as MRDIMM Gen2 at 12,800 MT/s in 2026 to 2027 [16]. Where a supplier's own roadmap and a supply-chain press report disagree by three years, the roadmap is the better guide to when parts will actually exist. Claims circulating online that DDR6 modules are available in 2026 are not supported by any primary source.

Low-power, graphics and stacked variants

The cell array is broadly the same across DRAM product families; the differences are almost entirely in the peripheral circuits, the packaging and the interface [1].

Family	Latest standard	Published	Headline rate	Typical use
LPDDR4	JESD209-4	25 August 2014 [12]	3200 MT/s	Phones, tablets
LPDDR5	JESD209-5	19 February 2019 [12]	6400 MT/s	Phones, edge AI
LPDDR5X	JESD209-5B	28 July 2021 [12]	8533 MT/s	Apple silicon unified memory, NVIDIA Grace
LPDDR6	JESD209-6	9 July 2025 [12]	10,667-14,400 MT/s	Announced; products from late 2020s [16]
GDDR5	JESD212C	February 2016 [13]	up to 8 Gbps/pin	Older GPUs
GDDR6	JESD250C [13]	-	11-20 Gbps/pin	Consumer GPUs, inference cards
GDDR7	JESD239	March 2024 [14]	up to 32 Gbps/pin, 192 GB/s per device	RTX 50 series, NVIDIA Rubin CPX
HBM3E	JESD238A (the HBM3 revision under which HBM3E parts are sold)	January 2023	~9.6 Gbps/pin, ~1.2 TB/s per stack	AI accelerators
HBM4	JESD270-4	April 2025	8 Gbps/pin, 2 TB/s per stack	2026 accelerators

The two HBM rows are included for comparison only. The dedicated High Bandwidth Memory article covers those standards, their packaging and the supplier race in detail.

LPDDR trades capacity and error correction for energy per bit by shortening the wires: the package sits next to the processor rather than on a socketed module. That is why it has become the second memory tier on AI systems, holding weights and context that do not fit in HBM but would be too slow to fetch from storage. GDDR7 also abandoned binary signalling: its PAM3 interface uses three levels to transmit three bits over two cycles where NRZ transmits two, and it doubles the number of independent channels, from two in GDDR6 to four in GDDR7 [14]. That is a sign that per-pin rates are running into the same signal-integrity ceiling that pushed HBM4 to widen its bus rather than speed it up [14].

HBM as DRAM in a stacked package

HBM exists for one reason: to put more DRAM pins closer to the processor than a printed circuit board allows. Instead of a 64-bit channel on a motherboard trace, an HBM stack presents 1024 bits per stack (2048 in HBM4) over a silicon interposer, at a fraction of the energy per bit, by moving the memory to within a few millimetres of the logic die.

The cost of that is paid in silicon area and yield. Each DRAM die in a stack has to carry more than 1,200 signal wires through it as through-silicon vias, and the area those consume makes an HBM die roughly twice the size of an ordinary DDR die of the same capacity [1]. That single fact is the mechanism behind the 2025 and 2026 supply squeeze described below: every gigabyte of HBM consumes about twice the wafer area of a gigabyte of DDR5, so shifting capacity into HBM removes conventional DRAM bits from the market faster than the HBM bit count alone would suggest. Stacking, alignment and binning add further yield loss on top. For the generation-by-generation detail see HBM3e and HBM4.

Manufacturing and market structure

DRAM manufacturing is a capital-intensive commodity business with almost no product differentiation at the interface level, which over four decades has driven relentless consolidation. More than twenty manufacturers produced DRAM in the mid-1990s, with the top ten sharing about 80% of the market; SemiAnalysis put the top three above 95% of the market in September 2024 [1]. TrendForce's supplier table for the first quarter of 2026 sums to 89.7% for the same three companies [20]; the two figures come from different trackers with different definitions of the total market and should not be treated as a trend line. Japanese makers first exceeded US market share in 1981 and peaked near 80% in 1987; Korean makers passed Japan in 1998 [1]. Each transition happened because a rapid generational cadence on a comparatively simple process gave a well-capitalised newcomer a way in. As scaling slowed, that door narrowed.

The three incumbents are Samsung, SK hynix and Micron Technology. TrendForce's quarterly revenue tracking gives the shape of the oligopoly, with the caveat that its supplier table and any given analyst's total-market definition are not the same measurement:

Quarter	Industry revenue	Samsung	SK hynix	Micron
4Q25	$53.58bn (+29.4% QoQ)	$19.30bn, 36.0%	$17.22bn, 32.1%	$11.98bn, 22.4%
1Q26	$97bn (+81% QoQ)	$37.32bn, 38.5%	$27.98bn, 28.8%	$21.75bn, 22.4%

Source: TrendForce, 26 February 2026 [19] and 1 June 2026 [20].

The fourth entrant is CXMT, founded in Hefei in 2016 on DRAM patents bought out of the collapse of Qimonda. Reuters reported in July 2026, citing CXMT's IPO prospectus, that the company held about 7.7% of the DRAM market in 2025, making it the world's fourth-largest DRAM maker, though it remains behind the incumbents in HBM [28]. CXMT is also technically interesting for a reason unrelated to its size: it adopted a 4F squared cell with vertical channel transistors in an 18 nm DRAM demonstrated in late 2023, ahead of any of the three incumbents [1]. SemiAnalysis read that as a sign of weakness rather than leadership, on the argument that Samsung, SK hynix and Micron were still able to shrink conventional 6F squared cells and so were not forced into the harder architecture [1]. Chinese DRAM capacity is also entangled with export controls: United States rules introduced in December 2024 restrict exports to China of high-bandwidth memory above a specified bandwidth density, which is what makes CXMT's DRAM progress the ceiling on domestic Chinese accelerator memory. See China's semiconductor industry for the wider policy picture.

The capex cycle

DRAM is the textbook cyclical industry, and it is cyclical for a structural reason: supply can only be added by building a fab, which is lumpy, slow and enormous, while demand moves in months. TechInsights puts the interval from groundbreaking to meaningful output at three to five years, and longer where permitting or tool delivery intervenes, with further time needed to reach high yields on a new node [23]. Because every supplier reads the same demand signal at the same time, capacity tends to arrive together, and prices collapse together.

The historical amplitude is large. Worldwide DRAM sales fell from $99.4 billion in 2018 to an expected $62 billion in 2019 according to IC Insights, a 38% decline in a single year with no change in the underlying technology [2]. The current cycle runs the other way and is sharper still: a single quarter, 1Q26, produced $97 billion of DRAM revenue, close to the whole of 2018 [20].

Slow density scaling has made the cycle worse, not better. In the era when cost per bit fell quickly, a price decline could be absorbed by the next node. With density improving only about 2 times per decade, there is no cost cushion, so pricing swings pass almost directly into margins [1]. That is also why only very large companies remain: the losses in a trough are survivable only for a balance sheet that can fund the next node anyway.

DRAM and the memory wall

The term memory wall predates the current AI boom, but transformer inference is the workload that made it a first-order commercial problem. Generating one token requires reading the model's weights, or at least the active experts' weights, and the entire KV cache for the sequence, and doing comparatively little arithmetic per byte read. Throughput is therefore set by bytes per second out of memory, not by floating-point operations per second, and the gap between the two has widened continuously: 3.0x per two years for peak FLOPS against 1.6x per two years for DRAM bandwidth [5]. Most of the familiar inference optimisations on an AI accelerator are responses to this: quantization shrinks the bytes that have to move, FlashAttention restructures attention to avoid materialising intermediates in DRAM, KV-cache compression and eviction attack the fastest-growing term, and batching amortises a single weight read across more tokens.

Bandwidth per unit of compute is the metric that matters, and it has been falling for a decade of accelerator generations. The industry's response has been to buy bandwidth with packaging rather than with memory technology: wider buses, shorter wires, more stacks per package. This works, and it is expensive.

Why HBM commands a premium

HBM is priced far above conventional DRAM for reasons that are mostly manufacturing rather than scarcity rent. It uses about twice the die area per bit for TSVs [1], it requires 8 to 16 dies to be thinned, aligned and bonded without a single fault, and it can only be attached to a processor through advanced packaging such as TSMC's CoWoS. SemiAnalysis estimated in September 2024 that HBM cost three times or more per gigabyte than standard DDR5, that HBM accounted for more than half the manufacturing cost of an NVIDIA H100, and that the figure rose above 60% for Blackwell [1]. TrendForce put the HBM3e price premium at more than four times DDR5 as of the second quarter of 2025 [22].

That premium proved unstable, and in an instructive direction. In October 2025 TrendForce forecast that DDR5 profitability would surpass HBM3e from the first quarter of 2026, because HBM3e supply had become competitive across three qualified suppliers while conventional DRAM was in acute shortage [22]. By June 2026 the reversal was visible in the revenue tables: TrendForce attributed SK hynix's below-market growth in 1Q26 partly to declining HBM contract prices, while Samsung, weighted toward server DDR5 and RDIMMs, grew 93.4% quarter on quarter [20]. The lesson is that HBM's premium is a function of qualification scarcity, not a permanent property of stacked DRAM.

The 2025-2026 supply squeeze

Through 2025 and into 2026 the DRAM market entered what TechInsights described in June 2026 as what may become the most pronounced supply shortage in the memory market's history [23]. The mechanism was straightforward. AI datacenter demand for HBM and for high-density server modules grew faster than wafer capacity, suppliers reallocated their most advanced nodes and their new capacity toward HBM and server products, and because an HBM die costs roughly twice the area of a DDR die per bit [1], the reallocation removed conventional DRAM bits from the market disproportionately. PCs and phones could not absorb the shortage by specifying less memory, because they already ship at the minimum configurations buyers expect, and AI operators could not either, because reducing memory directly reduces what a cluster can serve [23].

Prices went nearly vertical. TrendForce revised its 1Q26 forecast for conventional DRAM contract prices from 55 to 60% growth up to 90 to 95% quarter on quarter, with PC DRAM above 100%, server DRAM around 90%, and LPDDR4X and LPDDR5X around 90% each, describing several of these as the steepest quarterly increases on record [21]. The realised figure came in at 93 to 98% [20], and TrendForce projected a further 58 to 63% increase for the second quarter of 2026 [20]. TechInsights argued in June 2026 that the shortage is structural rather than an inventory artefact, that new fabs take three to five years to matter, and that meaningful price declines are therefore unlikely before capacity catches up [23].

For AI operators the practical consequences are that memory has become a scheduling constraint as much as a cost line, that securing multi-year supply matters more than negotiating unit price, and that the cost of a data center buildout is now materially exposed to a commodity cycle that has nothing to do with accelerators.

Research directions

The industry is pursuing several successors to the conventional 6F squared stacked-capacitor cell, at very different levels of maturity. The list below runs from an architecture already in production silicon to ideas that exist only in research, and the labels matter: DRAM roadmaps are unusually prone to being read as product announcements.

4F squared cells and vertical channel transistors (in silicon at one supplier). Moving from a 6F squared to a 4F squared cell layout gives a theoretical 30% density gain without shrinking the feature size at all, because the cell footprint drops to two thirds [1]. Achieving it requires standing the access transistor up vertically so that the bitline contact, channel and capacitor contact stack in a single column rather than spreading horizontally. CXMT used this arrangement in an 18 nm DRAM demonstrated in late 2023 [1]; the three incumbents have it on their roadmaps but had not made it their mainstream cell as of the most recent public roadmap updates [24].

3D DRAM (roadmap, around 2030). The idea is the one that saved NAND: stop shrinking laterally and stack cell layers vertically instead. DRAM is much harder to stack than NAND because each cell needs a capacitor and a low-leakage access transistor rather than a charge-trap layer, and because the sense path must remain short. SK hynix's roadmap presented in November 2025 places 3D DRAM at around 2030 with no published specifications [16]. TechInsights' Q3 2026 DRAM technology roadmap tracks 3D DRAM alongside X-DRAM, IGZO DRAM and vertical-channel-transistor 4F squared cells as the candidate architectures beyond conventional 6F squared scaling [24].

Capacitorless and IGZO cells (research). A 2T0C cell replaces the storage capacitor with a second transistor whose gate holds the charge, which removes the high-aspect-ratio etch problem entirely. It only works if the access transistor leaks almost nothing, which is why the research has converged on indium-gallium-zinc-oxide (IGZO) thin-film transistors, whose extremely low off-state current can hold a gate charge for a long time and would dramatically relax refresh requirements. TechInsights' Jeongdong Choe places prototypes of 2T0C capacitorless IGZO DRAM at around 2028 or later, as one of the approaches needed once 6F squared scaling ends near 10 nm [3]. No commercial product exists.

Processing in memory (demonstrated, not deployed). If the bottleneck is moving data between memory and compute, one answer is to do some of the compute inside the memory. Samsung announced HBM-PIM in February 2021, placing a DRAM-optimised AI engine inside each memory bank of an HBM2 stack, and claimed more than twice the system performance with more than 70% lower energy consumption on memory-bound workloads, with no hardware or software changes required of the host [25]. SK hynix followed in February 2022 with GDDR6-AiM, a GDDR6 die with computation added, claiming certain computations run 16 times faster and 80% less power at 1.25 V instead of 1.35 V, presented at ISSCC 2022 [26]. SK hynix has continued to develop the accelerator card built from these parts, AiMX, demonstrating at the AI Infra Summit in 2025 a disaggregated inference setup that runs memory-bound decode on four AiMX cards while compute-bound work stays on two H100 GPUs in the same Supermicro server [27]. The company's roadmap lists LPDDR6-PIM for around 2028 [16].

None of these PIM products has displaced standard DRAM in a mainstream accelerator, and the reason is ecosystem rather than silicon: a PIM part changes the programming model, and the AI software stack is written against a GPU-plus-HBM abstraction. The performance figures above are vendor claims on selected workloads, not independent measurements.

References

Patel, Dylan; Koch, Jeff; et al. "The Memory Wall: Past, Present, and Future of DRAM." SemiAnalysis, 3 September 2024. https://newsletter.semianalysis.com/p/the-memory-wall
LaPedus, Mark. "DRAM Scaling Challenges Grow." Semiconductor Engineering, 21 November 2019. https://semiengineering.com/dram-scaling-challenges-grow/
Choe, Jeongdong. "DRAM Scaling Trend and Beyond." TechInsights. https://www.techinsights.com/blog/dram-scaling-trend-and-beyond
Kim, Yoongu; Daly, Ross; Kim, Jeremie; et al. "Flipping Bits in Memory Without Accessing Them: An Experimental Study of DRAM Disturbance Errors." Proceedings of the 41st International Symposium on Computer Architecture (ISCA), 2014. https://people.inf.ethz.ch/omutlu/pub/dram-row-hammer_isca14.pdf
Gholami, Amir; Yao, Zhewei; Kim, Sehoon; Hooper, Coleman; Mahoney, Michael W.; Keutzer, Kurt. "AI and Memory Wall." IEEE Micro; arXiv:2403.14123, 21 March 2024. https://arxiv.org/abs/2403.14123
Wikipedia. "Synchronous dynamic random-access memory." https://en.wikipedia.org/wiki/Synchronous_dynamic_random-access_memory
Wikipedia. "DDR SDRAM." https://en.wikipedia.org/wiki/DDR_SDRAM
Wikipedia. "DDR2 SDRAM." https://en.wikipedia.org/wiki/DDR2_SDRAM
Wikipedia. "DDR3 SDRAM." https://en.wikipedia.org/wiki/DDR3_SDRAM
Wikipedia. "DDR4 SDRAM." https://en.wikipedia.org/wiki/DDR4_SDRAM
Wikipedia. "DDR5 SDRAM." https://en.wikipedia.org/wiki/DDR5_SDRAM
Wikipedia. "LPDDR." https://en.wikipedia.org/wiki/LPDDR
Wikipedia. "GDDR SDRAM." https://en.wikipedia.org/wiki/GDDR_SDRAM
Electronics Weekly. "JESD239 standard to improve GDDR7 memory performance in AI, gaming." 20 March 2024. https://www.electronicsweekly.com/news/products/memory/jesd239-standard-to-improve-gddr7-memory-performance-in-ai-gaming-2024-03/
TrendForce. "DDR6 Set for 2027 Mass Adoption as Memory Giants Reportedly Finalize Prototype Designs." 23 July 2025. https://www.trendforce.com/news/2025/07/23/news-ddr6-set-for-2027-mass-adoption-as-memory-giants-reportedly-finalize-prototype-designs/
Shilov, Anton. "SK hynix reveals DRAM development roadmap through 2031: DDR6, GDDR8, LPDDR6, and 3D DRAM incoming." Tom's Hardware, 5 November 2025. https://www.tomshardware.com/pc-components/dram/sk-hynix-reveals-dram-development-roadmap-through-2031-ddr6-gddr8-lpddr6-and-3d-dram-incoming
Micron Technology. "Micron Announces Shipment of 1-gamma DRAM: Pioneering Memory Technology Advancements for Future Compute Needs." Press release, 25 February 2025. https://www.globenewswire.com/news-release/2025/02/25/3032114/14450/en/Micron-Announces-Shipment-of-1%CE%B3-1-gamma-DRAM-Pioneering-Memory-Technology-Advancements-for-Future-Compute-Needs.html
Micron Technology. "1-Gamma DRAM technology." Product page. https://www.micron.com/products/memory/1gamma-dram-technology
TrendForce. "Price Rally Drives 4Q25 DRAM Revenue Up 29.4%; Samsung Regains No. 1 Market Share." 26 February 2026. https://www.trendforce.com/presscenter/news/20260226-12937.html
TrendForce. "Rapid Contract Price Surge Drives 1Q26 DRAM Industry Up 81% QoQ." 1 June 2026. https://www.trendforce.com/presscenter/news/20260601-13070.html
TrendForce. "Memory Price Outlook for 1Q26 Sharply Upgraded; QoQ Increases of All Product Categories to Hit Record Highs." 2 February 2026. https://www.trendforce.com/presscenter/news/20260202-12911.html
TrendForce. "Tight DRAM Supply to Boost DDR5 Contract Prices: Profitability in 2026 Expected to Surpass HBM3e." 29 October 2025. https://www.trendforce.com/presscenter/news/20251029-12758.html
TechInsights. "Why the AI Memory Shortage Could Keep DRAM and NAND Prices High for Years." 26 June 2026. https://www.techinsights.com/blog/why-ai-memory-shortage-could-keep-dram-and-nand-prices-high-years
TechInsights. "Memory Technology Roadmaps: Three Segments, Three Inflection Points." 9 July 2026. https://www.techinsights.com/blog/memory-technology-roadmaps-three-segments-three-inflection-points
Samsung Electronics. "Samsung Develops Industry's First High Bandwidth Memory with AI Processing Power." Press release, 17 February 2021. https://news.samsung.com/global/samsung-develops-industrys-first-high-bandwidth-memory-with-ai-processing-power
SK hynix. "SK hynix Develops PIM, Next-Generation AI Accelerator." Press release, 16 February 2022. https://news.skhynix.com/sk-hynix-develops-pim-next-generation-ai-accelerator/
SK hynix. "AI Infra Summit 2025: SK hynix Presents Updated AiM Solution." 1 October 2025. https://news.skhynix.com/ai-infra-summit-2025/
Reuters. "Explainer: What is CXMT and how did it become China's DRAM champion?" July 2026, via Yahoo Finance. https://finance.yahoo.com/technology/articles/explainer-cxmt-did-become-chinas-092012092.html

Editing: DRAM (Dynamic Random-Access Memory)