Quantum processor
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A quantum processing unit (QPU), also called a quantum processor, is the hardware component of a quantum computer that holds and manipulates qubits to perform quantum logic operations.[1][2] By analogy with the classical graphics processing unit (GPU) or tensor processing unit (TPU), a QPU is a specialised accelerator rather than a general-purpose processor: it executes quantum circuits dispatched by a classical host computer that handles compilation, error decoding, and measurement post-processing.[3] As of 2026, commercial and research QPUs are built from several competing physical modalities, including superconducting transmon circuits, trapped ions, neutral atoms, photons, silicon spins, and topological materials.[4][5] A more detailed companion overview is kept at QPU.
The terms "quantum processing unit" and "quantum processor" are used interchangeably in industry and academic literature. IBM and NVIDIA both define a QPU as the physical chip or chamber that contains the qubits, together with the immediate control hardware that enacts quantum gates.[1][2] The processor itself is only part of a full quantum computer, which also contains a dilution refrigerator (for superconducting and topological modalities) or a vacuum trap with laser systems (for ion and neutral-atom modalities), classical control electronics, and a runtime software stack.[3][6]
The pluralisation of the acronym follows the CPU/GPU/TPU pattern. A QPU is sometimes described as a "co-processor" to a classical host, a framing favoured by NVIDIA in its CUDA-Q and NVQLink architectures, which connect classical accelerators to one or more QPUs over low-latency links.[2][3] Vendors that do not build gate-model machines, notably D-Wave, instead market quantum annealers, which are specialised optimisation hardware that do not run arbitrary quantum circuits.[7]
A QPU differs from a classical processor in what it represents and how it computes. A classical register of N bits stores exactly one of 2^N possible values at a time, whereas N qubits can occupy a superposition spanning all 2^N basis states, and entanglement allows correlations between qubits that have no classical analogue.[1] Computation proceeds by applying a sequence of quantum gates (a quantum circuit) that rotate this state, followed by measurement, which collapses the state to classical bits with probabilities set by the circuit. This is why a QPU is not a faster CPU but a different kind of device: it offers a potential advantage only for problems whose structure maps onto interference between quantum amplitudes, such as factoring, certain simulations of quantum systems, and some sampling tasks.[1][4]
QPUs are not a single technology. Several broad modalities compete for the role of the dominant qubit substrate, and as of 2026 none has clearly won. Each trades off gate speed, coherence, connectivity, operating temperature, and manufacturability differently.
Superconducting circuits are the most widely deployed modality. Tiny Josephson-junction devices behave as artificial atoms when cooled to roughly 10 to 20 millikelvin in a dilution refrigerator, and microwave pulses drive gates in tens of nanoseconds.[1] Google (Sycamore, Willow), IBM (Eagle, Heron, Nighthawk, and the Loon research chip), and Rigetti (Ankaa) use this approach.[1][4][8][9] Strengths include fast gates and the ability to use semiconductor-style lithography; weaknesses include short coherence times relative to ions, limited nearest-neighbour connectivity on a chip, and the cost and complexity of large dilution refrigerators.
Trapped-ion machines suspend individual ions (commonly ytterbium or barium) in an electromagnetic trap and address them with laser or microwave pulses. IonQ and Quantinuum lead this approach. Quantinuum's H-series and its 2025 Helios system hold records for two-qubit gate fidelity, and ion systems typically offer all-to-all connectivity, meaning any qubit can be entangled directly with any other.[10][11] Ions are naturally identical and have long coherence times, but gates are slower than in superconducting devices, and scaling beyond tens of ions in a single trap requires shuttling ions between zones or networking traps together.[12]
Neutral-atom machines trap individual atoms (often ytterbium or rubidium) in arrays of optical tweezers and entangle them by exciting atoms to high-energy Rydberg states. Atom Computing demonstrated a 1,180-qubit array (with 1,225 trap sites) in October 2023, the first gate-based quantum system to exceed 1,000 qubits, and QuEra and Pasqal also pursue this modality.[13] Neutral-atom arrays can pack large numbers of qubits and can rearrange atoms to create flexible connectivity, but the technology is younger as a gate-based platform than superconducting or ion systems.
Photonic processors encode information in single photons or in squeezed states of light, and operate largely at or near room temperature, avoiding the large dilution refrigerators of superconducting machines (though single-photon detectors are still cryogenic). PsiQuantum, working with GlobalFoundries on a silicon-photonic chipset called Omega, and Xanadu (Borealis, Aurora) pursue this approach.[14][15] Photons interact weakly, which helps coherence but makes deterministic two-qubit gates difficult, so photonic designs rely on measurement-based schemes and must overcome optical loss.
Silicon spin qubits encode information in the spin of individual electrons or nuclei in silicon or silicon-germanium quantum dots. The appeal is compatibility with the existing semiconductor manufacturing base and very small device footprints. Intel has published work on this modality, including its Tunnel Falls research chip, and academic and startup groups (for example in Australia and the Netherlands) are active.[16] Spin qubits remain at smaller qubit counts than the leading superconducting and atom-based systems as of 2026.
Topological qubits aim to encode information non-locally in exotic quasiparticles, so that local noise cannot easily corrupt it. Microsoft announced Majorana 1 in February 2025, an eight-qubit device it described as the first quantum processor based on a "topological core," using an indium-arsenide and aluminium material it calls a topoconductor to host Majorana zero modes.[5][17] These claims drew significant skepticism from the physics community. The accompanying Nature paper demonstrated a single-shot parity measurement but stated that the measurements "do not, by themselves, determine whether the low-energy states detected by interferometry are topological," and outside physicists publicly questioned whether the devices host Majorana zero modes at all.[18][19] Topological quantum computing therefore remains a research bet rather than a demonstrated working modality as of 2026.
Quantum annealers, exemplified by D-Wave's Advantage system with more than 5,000 qubits, are not gate-model QPUs. They solve optimisation problems by encoding them into an energy landscape and exploiting quantum tunnelling to seek low-energy states, and they cannot run arbitrary quantum circuits, which is why they are usually treated as a distinct class of hardware.[7]
The table below summarises the main gate-model modalities and representative organisations pursuing each. Operating-temperature and connectivity entries describe the typical character of each platform rather than any single machine.
| Modality | Qubit carrier | Typical operating regime | Native connectivity | Notable organisations |
|---|---|---|---|---|
| Superconducting transmon | Josephson-junction circuit | Dilution refrigerator, ~10-20 mK | Nearest-neighbour on chip | Google, IBM, Rigetti |
| Trapped ion | Ytterbium or barium ion | Vacuum trap, lasers | All-to-all within a trap | IonQ, Quantinuum |
| Neutral atom | Rubidium or ytterbium atom | Optical tweezers, lasers | Reconfigurable | Atom Computing, QuEra, Pasqal |
| Photonic | Photon / squeezed light | Mostly room temperature | Measurement-based | PsiQuantum, Xanadu |
| Silicon spin | Electron / nuclear spin in a quantum dot | Cryogenic, ~1 K range | Nearest-neighbour | Intel, academic groups |
| Topological (claimed) | Majorana zero mode | Dilution refrigerator | Designed for surface-code layout | Microsoft |
No single number captures how good a QPU is, and headline qubit counts can be misleading, because a large number of low-fidelity qubits may be less useful than a smaller, cleaner machine. Several metrics are used together.[11][20]
Several composite benchmarks try to fold these into one number. IBM's quantum volume measures the size of the largest square random circuit a machine can run successfully and grows as 2 raised to that size.[22] IBM also reports CLOPS (circuit layer operations per second) for speed.[22] IonQ promotes algorithmic qubits (#AQ), defined roughly as the largest number of near-perfect qubits a typical program can use, measured on application-style circuits rather than purely random ones.[23] Google's preferred demonstration metric is random circuit sampling (RCS), a task chosen to be hard for classical computers.[4][24] Because vendors emphasise different benchmarks, cross-vendor comparison requires care.
Physical qubits are noisy, so the long-term path to useful quantum computing runs through quantum error correction (QEC), in which many physical qubits are combined into a smaller number of more robust logical qubits. The key theoretical idea is the error-correction threshold: if the physical error rate falls below a code-specific threshold, then making the code larger reduces the logical error rate rather than introducing more error than it fixes.[4][24]
In December 2024, Google reported the first convincing demonstration of operating below threshold with a surface code on its 105-qubit Willow chip: as it scaled the code from a 3x3 to a 5x5 to a 7x7 grid of qubits, the logical error rate dropped by roughly half at each step, the behaviour expected when error correction is working.[4][24] Google also reported that Willow performed a random-circuit-sampling computation in under five minutes that it estimated would take one of the fastest classical supercomputers on the order of 10^25 years, although such sampling benchmarks have no direct practical application.[4]
Other groups pursue QEC on different hardware. In November 2024, Microsoft and Atom Computing reported creating and entangling 24 logical qubits on a neutral-atom system using Microsoft's qubit-virtualisation software, which they described as the largest number of entangled logical qubits reported at the time, alongside error-detection demonstrations on 28 logical qubits.[25] Quantinuum's Helios reported operating dozens of logical qubits, including configurations described as 48 fully error-corrected and 50 error-detected logical qubits, built from its 98 physical ions.[11]
Approaches to QEC codes are also diverging. The surface code, used by Google, is robust but demands many physical qubits per logical qubit because it relies on local, nearest-neighbour connectivity. IBM has pivoted to quantum low-density parity check (qLDPC) codes, which exploit longer-range connections to cut the physical-qubit overhead by up to about 90 percent relative to surface codes; its 2025 Loon research chip was built to demonstrate the long-range "c-couplers" and components such codes require, with real-time decoding reported in under 480 nanoseconds.[9][20] Microsoft has separately published work on four-dimensional QEC codes.[26]
The table below lists representative QPUs with figures reported by vendors and peer-reviewed sources. Figures are as published; vendors emphasise different metrics, so entries are not directly comparable.
| QPU | Vendor | Qubits | Modality | Date | Note |
|---|---|---|---|---|---|
| Sycamore | 53 | Superconducting | 2019 | Random-circuit-sampling claim of quantum advantage[27] | |
| Eagle | IBM | 127 | Superconducting | 2021 | First gate machine over 100 qubits[8] |
| Osprey | IBM | 433 | Superconducting | 2022 | [8] |
| Borealis | Xanadu | 216 modes | Photonic | 2022 | Gaussian boson sampling[15] |
| Condor | IBM | 1,121 | Superconducting | 2023 | First over 1,000 superconducting qubits[8] |
| Gen-2 array | Atom Computing | 1,180 | Neutral atom | Oct 2023 | First gate-based system over 1,000 qubits[13] |
| Heron R2 | IBM | 156 | Superconducting | 2024 | Tunable couplers; basis of System Two[8] |
| Ankaa-3 | Rigetti | 84 | Superconducting | Dec 2024 | Median 99.5% two-qubit fidelity[^9b] |
| Willow | 105 | Superconducting | Dec 2024 | Below-threshold surface-code error correction[4][24] | |
| Majorana 1 | Microsoft | 8 | Topological (claimed) | Feb 2025 | Topological-qubit claim disputed by reviewers[5][18][19] |
| Helios | Quantinuum | 98 | Trapped ion | Nov 2025 | Two-qubit fidelity 99.921%[11] |
| Nighthawk | IBM | 120 | Superconducting | Nov 2025 | 218 tunable couplers; targets 5,000 two-qubit gates[20] |
| Loon | IBM | research | Superconducting | Nov 2025 | Demonstrator for fault-tolerant components[20] |
Several of these milestones reset the leading qubit counts within months of one another, a pattern characteristic of the early commercial phase of the field.
IBM publishes a detailed public roadmap. Its November 2025 Nighthawk processor carries 120 qubits linked by 218 next-generation tunable couplers in a square lattice (over 20 percent more couplers than Heron), which IBM says lets users run circuits roughly 30 percent more complex while targeting up to 5,000 two-qubit gates, rising in later Nighthawk releases.[20] Its experimental Loon chip is built to validate the architecture for qLDPC-based fault tolerance.[20] IBM's longer roadmap targets a series of named systems: Kookaburra (2026), Cockatoo (2027), and Starling, planned for 2029 as a machine able to run about 100 million quantum operations across 200 logical qubits, followed by Blue Jay (2033 and beyond) scaling toward 2,000 logical qubits and roughly a billion operations.[9][20] IBM has said it expects to demonstrate a verified quantum advantage by the end of 2026.[20]
Google's focus has shifted from raw qubit count toward error correction and quality. Its 105-qubit Willow chip, fabricated at a dedicated facility in Santa Barbara, provided the below-threshold QEC result described above and is positioned as a step on a roadmap toward a large fault-tolerant machine.[4][24]
The two leading trapped-ion companies pursue different strategies. Quantinuum's Helios, launched in November 2025, uses 98 barium ions (a switch from ytterbium) in a quantum charge-coupled-device (QCCD) architecture with all-to-all connectivity and the highest gate fidelities released to market at launch, and integrates with NVIDIA accelerators via NVQLink for real-time decoding.[11] IonQ markets its Forte and Forte Enterprise systems on the algorithmic-qubit metric and has published an aggressive roadmap toward far larger qubit counts later in the decade; its roadmap figures are targets rather than delivered hardware and should be read as such.[28]
PsiQuantum unveiled its Omega photonic chipset in February 2025, fabricated on 200-millimetre silicon-on-insulator wafers by GlobalFoundries and designed as a building block for a future million-qubit machine, and has announced plans for large "Quantum Compute Centers" in Brisbane and Chicago.[14] Atom Computing, working with Microsoft, has described plans for an on-premises neutral-atom system supporting on the order of 50 logical qubits.[25] As with all such roadmaps, the gap between announced targets and demonstrated, benchmarked hardware is the key thing to watch.
QPUs are at most tangentially relevant to current artificial intelligence work. Mainstream production AI as of 2026 runs on classical GPU and TPU silicon, not on QPUs, and there is no quantum processor on which today's large neural networks could be trained.[1][2] The connection runs instead through quantum machine learning (QML), a research area that studies whether quantum hardware can speed up or improve machine learning subroutines.
Typical near-term QML proposals include variational quantum circuits (parameterised circuits trained much like neural networks), quantum kernel methods, and quantum-enhanced sampling. These are designed to run on a hybrid loop in which a classical CPU or GPU host iteratively updates parameters that a QPU then evaluates.[29] As of 2026, no QML system has demonstrated a practical advantage over classical machine learning for a real-world task at the scale of large language models or production image classifiers.[29]
The central caveat is noise. The field is in what John Preskill in 2018 named the NISQ era (noisy intermediate-scale quantum), in which devices have between roughly 50 and a few thousand physical qubits and lack full error correction.[30] In this regime, the error budget allows only short computations, and gradient-based training of variational circuits suffers from barren plateaus, where loss landscapes become exponentially flat as the system grows, making optimisation increasingly difficult.[29] These limitations are why claims of imminent quantum advantage for AI should be treated cautiously.
The below-threshold error-correction result on Willow, and the move toward logical qubits across several platforms, open a path to encoded qubits whose error rate falls as the code grows, which is a prerequisite for running the deep circuits that useful quantum algorithms require.[4][24] IBM's published roadmap targets 200 logical qubits by 2029 and larger fault-tolerant systems in the 2030s, after which quantum subroutines relevant to chemistry, optimisation, and possibly certain machine-learning tasks become more plausible.[9][20] Whether a useful quantum advantage for AI specifically will materialise on those timescales is an open research question, and on current evidence quantum processors are a complement to, not a replacement for, the classical accelerators that drive modern AI.