NVIDIA Groq LPX Rack

NVIDIA Groq 3 LPX is a rack-scale inference accelerator that NVIDIA introduced at GTC 2026, built around 256 Groq Language Processing Units and designed to sit beside Vera Rubin NVL72 racks as a dedicated decode engine.^[1][2] Often shortened to the "LPX rack," the system packs hundreds of small, SRAM-heavy chips that generate output tokens at very low latency while the Rubin GPUs handle the heavier prompt-processing work. It brings a dedicated LPU inference accelerator into NVIDIA's data center platform, and it is the most visible product to come out of the company's roughly $20 billion deal for Groq's inference technology in December 2025.^[3][4][6]

The chip itself is branded the Groq 3 LPU, the seventh processor in the Vera Rubin lineup alongside the Rubin GPU, Vera CPU, NVLink 6 switch, ConnectX-9 SuperNIC, BlueField-4 DPU, and Spectrum-6 Ethernet switch.^[1][5] NVIDIA describes the LPX as "co-designed with NVIDIA Vera Rubin NVL72," and the two systems are meant to be deployed together rather than sold as a standalone box.^[1] On August 24, 2026, NVIDIA said LPX had entered full production, superseding its earlier second-half target. NVIDIA named Nebius as the first AI cloud adopter and said Groq planned to follow among the earliest adopters.^[10] Full production did not itself mean that a public endpoint was live: Artificial Analysis described its launch-period access as a private demonstration deployment and said the rack would enter operation later in 2026.^[11]

Background: the Groq deal

The LPX traces directly back to NVIDIA's agreement with Groq, the inference-chip startup founded by former Google engineer Jonathan Ross. On December 24, 2025, CNBC reported that NVIDIA had struck a deal worth about $20 billion, which would make it NVIDIA's largest transaction to date, well past the $6.9 billion Mellanox acquisition in 2020.^[3][4] Rather than buying the company outright, NVIDIA structured the arrangement as a non-exclusive license for Groq's inference technology plus an acquihire of its leadership, with Ross, president Sunny Madra, and other senior staff moving to NVIDIA while Groq continued as a nominally independent entity.^[4] Groq had been valued at $6.9 billion after a $750 million funding round in September 2025, so the reported figure represented a steep premium.^[4]

Several outlets framed the LPX as the productization of that deal: customers who once might have rented Groq's cloud could now buy comparable silicon directly from NVIDIA, folded into the CUDA and Vera Rubin stack.^[2][6] NVIDIA's own materials do not dwell on the dollar figure, but they confirm that the Groq 3 LPU is "newly integrated" into the platform after the technology came over from Groq.^[1]

Architecture

The design philosophy behind the LPU is the same one Groq built its business on: keep the model weights and activations in fast on-chip SRAM instead of slower off-chip HBM4, and use a deterministic, compiler-orchestrated execution model so there is no dynamic hardware scheduling.^[2][6][9] Each Groq 3 LPU carries 500 MB of on-chip SRAM running at 150 TB/s, versus the roughly 22 TB/s of HBM4 bandwidth on a Rubin GPU.^[6][7] The tradeoff is capacity: a single LPU holds very little memory, so NVIDIA gangs many of them together to fit a model.^[7]

NVIDIA's March 16, 2026 technical blog post, by Kyle Aubrey and Farshad Ghodsian, describes the chip in more detail. Compute and communication are organized around 320-byte vectors as the unit of work, and three classes of execution module handle different operations: matrix execution modules (MXM) for dense multiply-accumulate work, vector execution modules (VXM) for pointwise arithmetic, type conversion, and activation functions, and switch execution modules (SXM) for permutation, rotation, distribution, and transposition of vectors. The 500 MB of SRAM sits in what NVIDIA calls the MEM block, "a flat, SRAM-first memory architecture" in which the compiler and runtime, rather than a hardware-managed cache, place the active working set of weights, activations, and KV state and move data explicitly. Because that capacity is finite, larger models are spread across many LPUs with strategies such as layer-wise partitioning. Instead of dynamic hardware schedulers, the chips rely on what NVIDIA describes as a plesiosynchronous chip-to-chip protocol that cancels clock drift and lets hundreds of LPUs act as one coordinated system, which is the property NVIDIA credits for stable time-to-first-token and per-token latency at small batch sizes.^[9]

A full LPX rack contains 256 LPUs arranged as 32 liquid-cooled 1U compute trays, each holding 8 chips.^[2][5] NVIDIA's tray specification names the chips LP30 and says each tray also integrates a host processor and fabric expansion logic in a cableless design.^[9] At the rack level that adds up to 128 GB of total SRAM, about 40 PB/s of aggregate SRAM bandwidth, and 315 PFLOPS of FP8 compute, plus 12 TB of DDR5 for spillover.^[1][8] The chips talk to each other over Groq's RealScale chip-to-chip fabric, with 96 links per chip at 112 Gbps, giving 2.5 TB/s of bidirectional bandwidth per LPU and 640 TB/s of scale-up bandwidth across the rack.^[2][8][9] NVIDIA uses a cableless backplane spine of paired copper connections to wire the trays together.^[6]

The SRAM and DRAM figures answer different questions and should not be added together. The 128 GB is the on-chip SRAM that the compiler manages as working storage; the DRAM sits off-chip, behind the fabric expansion logic and the host CPU in each tray, and the product page describes it as being "for large models and workloads."^[8][9] The table reproduces NVIDIA's published numbers, which do not all multiply exactly: 32 trays at 9.6 PFLOPS is 307 PFLOPS against the 315 PFLOPS rack figure NVIDIA quotes, and the per-LPU compute figure is the tray figure divided by eight rather than a number NVIDIA publishes on its own.^[8][9] The Aug 24, 2026 blog post restates the rack-level view as "256 LP30 local processing units (LPUs)", "128 GB of total SRAM-based memory", and "96 C2C links per chip running at 112 Gbps each".^[13]

The whole system is built on NVIDIA's MGX modular rack architecture and is fully liquid-cooled, the same plumbing approach used for the Vera Rubin NVL72 it pairs with.^[1][2]

How it works with Vera Rubin

The LPX is not a replacement for the GPU. It is a specialist that takes over one slice of the inference pipeline. Large language model serving splits into two phases: a compute-heavy prefill stage that processes the input prompt, and a memory-bound decode stage that emits one token at a time. Decode is where latency hurts most, and where the LPU's bandwidth advantage pays off.^[2][6]

NVIDIA's scheme for splitting the work is called attention-FFN disaggregation, or AFD. Under AFD the Rubin GPUs run the attention layers over the KV cache during both prefill and decode, while the LPUs execute the feed-forward and Mixture of Experts expert layers.^[1][2][9] NVIDIA's product page puts it more simply: "Rubin GPUs and LPUs boost decode by jointly computing every layer of the AI model for every output token."^[8] The handoff is coordinated by NVIDIA Dynamo, the inference serving framework that routes prefill to GPU workers and then orchestrates the AFD loop, passing intermediate activations to the LPUs for the FFN and MoE work.^[2][9]

The AFD decode loop

The March 16 post is NVIDIA's fullest public description of the split. It treats prefill and decode as different problems: prefill "is dominated by ingesting large inputs and building the KV cache", which suits the NVL72's dense parallel compute and memory capacity, while decode "is a repeated per-token loop, and different parts of that loop stress different bottlenecks." In the Vera Rubin architecture with LPX, NVIDIA says, "decode is best thought of as a two-engine loop": GPUs handle the decode work that benefits from throughput and large memory capacity, "such as full-context attention over the accumulated KV cache", and LPX "accelerates latency-sensitive execution within decode, such as sparse MoE expert feed-forward networks (FFNs) and other pointwise operations." The post then defines the term: "This split, often described as decode phase disaggregation or attention-FFN disaggregation (AFD), separates attention from FFN within decode and exchanges intermediate activations for each token, so each engine runs the part of the loop it is best suited to execute."^[9]

The August 24 follow-up post describes the same configuration in terms of where the memory lives: "Vera Rubin NVL72 computes attention and holds the KV cache in DRAM, while Groq 3 LPX executes the FFN layers. Only intermediate tokens are sent between racks, once per full-attention layer."^[13] That arrangement is the reason the LPU's small memory is not a limitation in this mode. The growing per-request KV cache stays in the GPUs' memory, and the LPUs hold the fixed-size FFN and expert weights plus the activations in flight.^[9][13] The March post also positions the split against the broader trend it calls the shift toward interactive inference, listing four forces that make throughput-optimized serving a poorer fit for interactive work: latency as a product feature, longer reasoning outputs, prefix caching (which shrinks prefill and raises the share of request-specific decode work), and longer contexts.^[9]

Figure 7: Dynamo orchestrating heterogeneous compute

The March post's Figure 7, captioned "Dynamo orchestrates heterogeneous compute," is the diagram most often reproduced when the LPX pairing is discussed. It is titled "NVIDIA Dynamo Orchestrates Heterogeneous Compute" with the subtitle "KV-aware routing for prefill and disaggregated decode (ATTN <-> FFN)". A green NVIDIA Dynamo bar spans two rack drawings. On the left, a Vera Rubin NVL72 labelled "72 Rubin GPUs" has two highlighted groups of trays, "Prefill GPUs" and "Decode GPUs (ATTN)"; a KV cache icon beside the rack connects to both groups by arrows labelled "NVLink or Ethernet", showing the cache built by the prefill GPUs and consumed by the decode GPUs. On the right, a Groq 3 LPX labelled "256 LPUs" has one large highlighted block, "Decode LPUs (FFN)". A double-headed arrow between the decode GPUs and the decode LPUs is labelled "Interim Decode Activations" and "Repeat per token", with "Ethernet" marked as the link.^[9] The diagram circulated again in September 2026 when Joe Fioti of the compiler startup Luminal attached it to a widely shared explainer arguing that AFD is the technique that lets SRAM-only accelerators serve long-context workloads because the KV cache never has to fit in SRAM; the post also asserted, without an NVIDIA source, that Cerebras was pursuing the same approach through its AMD and AWS partnerships, which those companies' announcements describe as prefill-decode splits (Trainium or Helios for prefill, the Cerebras system for decode) rather than attention-FFN splits.^[21][23][24]

Dynamo's role, and what the public code shows

NVIDIA's account of the software layer is specific. Making heterogeneous decode practical, the March post says, "requires software that can classify requests, route work by latency targets, move intermediate activations with low overhead, and keep tail latency stable under bursty, variable traffic," and Dynamo "provides that orchestration layer by coordinating disaggregated serving and disaggregated decode across heterogeneous backends." In practice, "Dynamo routes prefill to GPU workers to process the large context and build the KV cache. During decode, Dynamo orchestrates the AFD loop where GPUs run attention over the accumulated KV cache, intermediate activations are handed off to LPUs for FFN/MoE execution, and outputs return to the GPUs to continue token generation." The post credits KV-aware routing, low-overhead transfers, and latency-target-driven scheduling with keeping interactive sessions out of long queues and holding tail latency steady as concurrency changes, and it points readers to a GTC session, "The Future of AI Inference", for an explainer on AFD.^[9][22]

Those statements describe NVIDIA's deployment, not a feature that can be inspected in Dynamo's open-source repository. GitHub searches of ai-dynamo/dynamo on September 6, 2026 for AFD, attention-FFN, LPU, LPX, and Groq found no merged AFD serving mode. A pull request titled "feat(sglang): Add AFD (Attention-FFN Disaggregation) infrastructure", which added ATTENTION and FFN entries to the disaggregation-mode enum, placeholder handlers, and a design document as a "Phase 1" (its 26-file diff also carried prototype transfer, benchmark and test modules), was opened and closed unmerged on February 25, 2026.^[15] A user request for an AFD usage guide, opened in November 2025, was closed as not planned on May 26, 2026, with a maintainer replying that "a dedicated AFD usage hub isn't on the near-term docs roadmap."^[16] The LPX pairing does appear in a design proposal opened on August 27, 2026, for native external speculative decoding with independently scaled target and draft worker pools, which includes "an LPX adapter boundary"; that proposal covers the draft-model configuration described below, not AFD.^[20] The most concrete public AFD work in the Dynamo organization is in the aiconfigurator planning tool rather than the serving runtime: a feature issue opened April 22, 2026 set out to model AFD "alongside aggregated and P/D-disaggregated" modes and support "GPU+LPU heterogeneous deployment analysis", while listing runtime AFD serving and LPU profiling data as non-goals, and AFD estimate and default CLI modes were merged on June 8 and August 5, 2026.^[17][18][19] For the moment, then, "Dynamo orchestrates the AFD loop" rests on NVIDIA's own posts.

Three ways to pair the racks

The August 24 post, by Seth Weidman, Kirthi Devleker, and Andrew Ling, presents AFD as one of several serving configurations rather than the only one. It lists three ways to combine Groq 3 LPX with Vera Rubin NVL72, "all of these" chosen so that "each rack [can] focus on the portion of the workload it can best execute."^[13]

The same post shows, as its Figure 11, a projection for "a scaled-up GPT-OSS model to 2 trillion parameters" running on NVL72 plus LPX, with a footnote that "GPT-OSS 2T is a scaled-up version of the GPT-OSS 120B model." The figure is a projection, not a measurement.^[13]

Speculative decoding

The third configuration builds on a role the March post had already sketched. Speculative decoding uses a small draft model to propose several tokens that a larger target model verifies in parallel. NVIDIA argues that the LPU's deterministic execution and SRAM bandwidth make it "well-suited to act as the draft-generation engine", running ahead of a verifier on Rubin GPUs, which "remain highly efficient for large-model execution tasks such as prefill, attention processing, and token verification." The result, per the post's Figure 8, is speculative decoding spread across heterogeneous processors instead of running draft and target on the same hardware.^[9]

Physically, an LPX rack is meant to stand next to a Vera Rubin NVL72 rack and connect to it over a Spectrum-X interconnect, so the two systems behave like one disaggregated inference machine.^[7] Multiple LPX racks can be ganged together to serve larger models or higher concurrency.^[7] Because the LPU operates as an accelerator under the existing CUDA stack, NVIDIA says computation is offloaded to it transparently on a per-token basis, without developers having to rewrite their serving code.^[2]

Performance and economics

NVIDIA's headline claim is that an LPX-plus-Vera-Rubin configuration delivers up to 35 times higher inference throughput per megawatt and up to 10 times more revenue opportunity for trillion-parameter models, compared with a GB200 NVL72 Blackwell system.^[1][2] These are NVIDIA's own projections: the product page labels the throughput chart "Projected performance subject to change" and the revenue figure "Projected revenue based on AI factory throughput per gigawatt and estimated cost-per-million-tokens tiered pricing model."^[8] The March post states the 35x figure at an operating point of 400 tokens per second per user, using a 2-trillion-parameter MoE model with a 400K input context as its premium-tier example, and says Vera Rubin alone reaches up to 5x more revenue per megawatt than GB200 NVL72, rising to 10x with LPX for the most latency-sensitive workloads.^[9] The pitch is aimed squarely at agentic workloads and million-token context windows, where models reason over long inputs and users expect fast, steady token streams.^[1][8]

The public performance evidence covers different scopes and should not be treated as one benchmark. In live coverage of NVIDIA's Hot Chips presentation, ServeTheHome reported NVIDIA's rack-level claim that a single 256-LPU rack decoded 11,000 tokens per second on Gemma 4 31B.^[14] The report did not specify context length, batch size, precision, or concurrency for that figure, so it is not directly comparable with the endpoint test below. The same report described the design as offloading "the attention portion of the decode process back to the GPUs, making decode a disaggregated process."^[14]

Artificial Analysis separately measured a median 3,431 output tokens per second with Gemma 4 31B (Reasoning) at 100K input context, and 3,382 at 10K, on an NVIDIA-hosted private, pre-release endpoint.^[11][13] The 100K result was the median of 50 sequential requests at concurrency one through Google Cloud Private Service Connect. Artificial Analysis used the o200k_base tokenizer to normalize token counts; its methodology defines output speed after the first token arrives.^[12][13] Artificial Analysis said it ran its standard 1K, 10K, and 100K input-length prompts and that output speed "was maintained between the 10k and 100k input sequence lengths tested"; NVIDIA's post attributes the flat profile to the LPU's deterministic architecture and high tensor parallelism, and says that testing by both parties "confirmed that the NVIDIA configuration for both of these benchmarks had no loss of precision or model quality in its outputs."^[11][13] The comparison chart used 14-day medians from shared production serverless endpoints for the other providers, so the roughly fourfold gap shown there was not a like-for-like public-service or load test.^[13]

NVIDIA also ran the open SPEED-Bench coding evaluation on the same model and LPX system. It reported a median 4,767 output tokens per second and a P80 of 5,520, and said 20 percent of the tested tasks exceeded 5,500 tokens per second.^[13] That was a vendor-run workload result, not part of Artificial Analysis's endpoint measurement. NVIDIA's own framing of what the speed means is an agentic-coding example: at the measured 100K-context rate, decoding 5,000 tokens "takes about 1.5 seconds versus 50 seconds at 100 tokens per second", with the post adding that "today's most popular agentic tools run closer to 60 tokens per second."^[13] None of these results establishes public pricing, time to first token, end-to-end agent completion time, or performance under multi-user load.

The August post also explains why NVIDIA believes the rack holds its speed at long context. Serving a model above 3,000 tokens per second per user while managing a 100K-token KV cache means running tensor parallelism at very small batch sizes, where the fixed cost of coordinating many tiny transfers can outweigh the time saved by splitting the work. NVIDIA breaks each transfer into "first bit latency" (choosing a link, synchronizing endpoints, arbitrating conflicts) and transfer time, and argues that the LPX compiler's clock-cycle-level schedule of every chip-to-chip transfer removes real-time arbitration, so LPUs "can send data on the clock cycle when it is ready, and consume the data on the clock cycle when it arrives." Links are point-to-point between LPU pairs, and each LPU can route for others. The compiler also overlaps communication with compute at the granularity of 320-byte vectors, sending 320-column slices of a matrix product as soon as they are complete rather than waiting for the whole operation.^[13]

The underlying economic argument remains about token rates and stability. NVIDIA says Groq's deterministic execution avoids scheduling jitter so per-token latency remains predictable.^[1] The Register noted that, depending on configuration, the economics could land around $45 per million tokens generated, though it also cautioned that software support was likely to be limited at launch.^[7] The $45 figure matches the "Premium" tier in NVIDIA's own throughput chart, whose tiers run from a free tier serving a Qwen-3 235B model with 32K KV-cached tokens to Premium ($45) and Ultra ($150) tiers serving a 2-trillion-parameter GPT-MoE model with 400K KV-cached tokens.^[8]

Reception and context

Coverage of GTC 2026 generally read the LPX as a strategic move rather than just a new SKU. Several analysts pointed out that by absorbing Groq's technology and reselling it inside its own platform, NVIDIA both neutralized a fast-rising inference competitor and extended its reach into the part of the market, low-latency token generation, where dedicated inference chips were starting to look like a genuine threat to GPUs.^[2][6] The Decoder described it as NVIDIA adding "a dedicated inference pipeline for the first time," and tied that directly to the company's quasi-acquisition of Groq.^[2]

It is worth keeping the two threads distinct. The December 2025 licensing-and-acquihire deal and the March 2026 LPX introduction are connected, but they are separate events: the deal moved the technology and people, and LPX was the first system NVIDIA productized from them. NVIDIA's August announcement added that manufacturing had reached full production, but the only named cloud deployment was still prospective, with Nebius identified as the first adopter.^[10][11] Many finer specifications, including the per-token economics and some networking details, come from technical journalism and NVIDIA's developer documentation rather than from a single press release.^[1][2][7]

References

1. ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8 ^9 ^10 ^11NVIDIA Newsroom, "NVIDIA Vera Rubin Opens Agentic AI Frontier," March 16, 2026. nvidianews.nvidia.com/...nvidia-vera-rubin-platform
2. ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8 ^9 ^10 ^11 ^12 ^13 ^14StorageReview.com, "NVIDIA Groq 3 LPX: Everything we know," March 18, 2026. storagereview.com/...groq-3-lpx-everything-we-know
3. ^1 ^2CNBC, "Nvidia buying AI chip startup Groq's assets for about $20 billion in its largest deal on record," December 24, 2025. cnbc.com/...groq-for-about-20-billion-biggest-deal
4. ^1 ^2 ^3 ^4The Motley Fool, "Nvidia's 'Acqui-Hire' of Groq Eliminates a Potential Competitor and Marks Its Entrance Into the Non-GPU, AI Inference Chip Space," December 28, 2025. fool.com/...groq-deal-acquisition-ai-inference-lpu
5. ^1 ^2Tom's Hardware, "Nvidia Groq 3 LPU and Groq LPX racks join Rubin platform at GTC," March 16, 2026. tomshardware.com/...of-the-ai-model-on-every-token
6. ^1 ^2 ^3 ^4 ^5 ^6 ^7The Decoder, "GTC 2026: With Groq 3 LPX, Nvidia adds dedicated inference hardware to its platform for the first time," March 17, 2026. the-decoder.com/...its-platform-for-the-first-time
7. ^1 ^2 ^3 ^4 ^5 ^6The Register, "Nvidia slaps Groq into new LPX racks for faster AI response," March 16, 2026. theregister.com/...nvidia_lpx_groq_3
8. ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8NVIDIA, "NVIDIA Groq 3 LPX: Inference Accelerator for Agentic AI" (product page). nvidia.com/...lpx
9. ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8 ^9 ^10 ^11 ^12 ^13 ^14 ^15NVIDIA Technical Blog, "Inside NVIDIA Groq 3 LPX: The Low-Latency Inference Accelerator for the NVIDIA Vera Rubin Platform," March 16, 2026. developer.nvidia.com/...nvidia-vera-rubin-platform
10. ^1 ^2NVIDIA Newsroom, "NVIDIA Groq 3 LPX Now in Full Production With World-Class Speed for Agentic AI," August 24, 2026. nvidianews.nvidia.com/...lass-speed-for-agentic-ai
11. ^1 ^2 ^3 ^4Artificial Analysis, "Artificial Analysis has measured 3,431 tokens/s on Gemma 4 31B via a private demonstration endpoint for NVIDIA Groq 3 LPX," August 25, 2026. x.com/...2092070577934925992
12. ^Artificial Analysis, "Artificial Analysis Benchmarking Methodology," accessed August 27, 2026. artificialanalysis.ai/methodology
13. ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8 ^9 ^10 ^11 ^12NVIDIA Technical Blog, "How NVIDIA Groq 3 LPX Unlocks Ultrafast Interactivity at Long Context on NVIDIA Vera Rubin," August 24, 2026. developer.nvidia.com/...ntext-on-nvidia-vera-rubin
14. ^1 ^2ServeTheHome, "NVIDIA's Groq 3 LPU Accelerators for Heterogeneous AI Compute at Hot Chips 2026," August 25, 2026. servethehome.com/...s-ai-compute-at-hot-chips-2026
15. ^GitHub, ai-dynamo/dynamo pull request #6570, "feat(sglang): Add AFD (Attention-FFN Disaggregation) infrastructure," opened and closed February 25, 2026. github.com/...6570
16. ^GitHub, ai-dynamo/dynamo issue #4653, "[FEATURE]: Detailed Usage Guide for AFD Support in Dynamo," opened November 27, 2025, closed May 26, 2026. github.com/...4653
17. ^GitHub, ai-dynamo/aiconfigurator issue #888, "[feat] Support AFD," opened April 22, 2026. github.com/...888
18. ^GitHub, ai-dynamo/aiconfigurator pull request #1129, "feat(afd): add AFD estimate mode," merged June 8, 2026. github.com/...1129
19. ^GitHub, ai-dynamo/aiconfigurator pull request #1323, "feat(afd): add AFD default CLI mode built on the v2 Task architecture," merged August 5, 2026. github.com/...1323
20. ^GitHub, ai-dynamo/dynamo issue #13889, "DEP: Native external speculative decoding with independent target and draft pools," opened August 27, 2026. github.com/...13889
21. ^Joe Fioti (@joefioti), "There's only one technique that will save SRAM-only chips: attention-feedforward disaggregation," X, September 4, 2026. x.com/...2095993586320019913
22. ^NVIDIA On-Demand, "The Future of AI Inference" (session listing), accessed September 6, 2026. nvidia.com/...other25-dynamoday09
23. ^Cerebras Systems, "AWS and Cerebras Collaboration Aims to Set a New Standard for AI Inference Speed and Performance in the Cloud" (press release), March 13, 2026. cerebras.ai/...awscollaboration
24. ^Cerebras Systems, "AMD and Cerebras Announce Industry-Leading Ultra-Low-Latency and High Throughput AI Inference Solution" (press release), July 23, 2026. cerebras.ai/...cy-and-high-throughput-ai-inference