NAND flash memory

NAND flash memory is the non-volatile storage technology that holds the data in solid-state drives, memory cards, USB sticks, phones and the flash tiers of a modern data center. A cell is a transistor whose threshold voltage can be shifted by trapping electrons in an insulated layer between its channel and its control gate. Because the trapped charge stays where it is without power, the stored value survives a power cut, which is the property that distinguishes flash from DRAM and SRAM. Fujio Masuoka's group at Toshiba, whose memory business is now Kioxia, presented NAND at the 1987 IEEE International Electron Devices Meeting, three years after the same group produced NOR flash; Kioxia's account of the decision is that NAND "had a smaller circuit scale and was more amenable to storage capacity expansion" ^[3][4].

The defining property of NAND is an asymmetry that almost nothing else in computing has. Data is read and written a page at a time (kilobytes to tens of kilobytes), but it can only be erased a block at a time (hundreds of pages in a modern part), and a page cannot be rewritten in place without erasing the whole block that contains it. Every awkward thing about solid-state storage follows from that one constraint: the flash translation layer, garbage collection, write amplification, over-provisioning, wear levelling, TRIM, and the fact that two drives built from identical dies can differ by an order of magnitude in sustained write performance.

For an encyclopedia of artificial intelligence NAND matters twice over. It is the substrate under everything that is not currently resident on an accelerator: training corpora, dataset shards, model checkpoints, vector indexes, and the spilled tiers of key-value caches. And since late 2025 it has been a binding commercial constraint on the AI buildout itself, because supply that used to go into consumer drives has been pulled into high-capacity enterprise SSDs. Combined revenue at the top five NAND suppliers rose 83.7% quarter on quarter in the first quarter of 2026, to more than 38.9 billion dollars, which TrendForce attributed mainly to shortage-driven price hikes ^[8].

The flash cell

A NAND cell is a MOS transistor with an extra electrode buried in the gate stack. In the original design that electrode is a floating gate: a conductive island of polysilicon, completely surrounded by oxide, sitting between the channel and the control gate. Electrons pushed onto the island raise the voltage that must be applied to the control gate before the transistor conducts. Reading a cell means applying a reference voltage to the control gate and observing whether current flows, which tells the sense circuitry which side of that reference the cell's threshold voltage lies on ^[5].

Charge is moved onto and off the island by Fowler-Nordheim tunnelling. Applying a large vertical field between the control gate and the channel bends the oxide energy barrier steeply enough that electrons tunnel through it, a current that Cai and colleagues model as proportional to the square of the oxide field times an exponential in its reciprocal ^[2]. NAND uses Fowler-Nordheim tunnelling for both program and erase. NOR flash, by contrast, programs by channel hot electron injection: a lateral field between source and drain accelerates channel electrons, and a vertical field from the control gate then drives the energetic carriers through the tunnel oxide, with erase still done by tunnelling ^[5]. Hot-electron programming is fast per cell but draws far more current, which is one reason it does not scale to the massively parallel page programming NAND depends on.

Programming is not a single pulse. Because the target threshold voltage has to be hit precisely, and precision matters more with every extra bit stored per cell, controllers use incremental step-pulse programming (ISPP): a short high-voltage pulse, a verify read, another slightly larger pulse, and so on until the cell passes verify, at which point further pulses are inhibited ^[2]. ISPP can only add charge. There is no mechanism to remove a few electrons from one cell, which is exactly why an in-place rewrite is impossible ^[2].

The conductive floating gate has since been replaced in production parts by an insulating charge-trap layer, and the flat array by a vertical one, for reasons set out below.

Why erase is a block operation

The name comes from the wiring. Cells in NAND are connected in series into a string, source to drain, like transistors in a NAND logic gate, with select transistors at each end connecting the string to a bit line and to ground. Reading one cell means driving every other cell in the string into a pass state so that it conducts regardless of its stored charge, and sensing the current through the whole chain. NOR wires each cell in parallel to a bit line with its own contact, which is what gives it random access and what makes it large: Micron's technical note puts the NAND cell at 4F squared against 10F squared for NOR, roughly 60% smaller, because "NOR Flash cells require a separate metal contact for each cell" ^[1].

Erase is a block operation because the erase field is applied through the shared body of the cells rather than through individual word lines, so every storage node in the block gives up its charge together. Programming can be selective, because it is driven from a particular word line and bit line; erasing cannot. Erasing sets all bits in the block to 1, and programming can only turn 1 bits into 0 bits ^[1].

The timing consequences are severe and asymmetric. Micron's comparison of a 2 Gb SLC NAND part against a 128 Mb NOR part gives first-byte random read at 25 microseconds for NAND against 0.075 microseconds for NOR, but block erase at 500 microseconds for NAND against a full second for NOR, and sustained sequential write of 7.5 MB/s against 0.25 MB/s ^[1]. Those are figures from a 2006 note revised in 2010 and describing SLC parts; modern TLC and QLC dies are much slower per operation, and the ratios rather than the absolute numbers are what carry forward.

NAND against NOR

Scroll sideways for more →

Figures from Micron's TN-29-19, comparing an MT29F2G08A SLC NAND against a TE28F128J3 NOR part; the note dates from 2006 and was last revised in April 2010 ^[1].

NOR won the embedded code-storage market and NAND won everything else, for reasons that are visible in that table. NOR is randomly addressable at byte granularity with a read latency measured in tens of nanoseconds, so a processor can fetch and execute instructions directly out of it. That capability, execute-in-place (XIP), is why NOR survives in boot ROMs, automotive electronic control units, industrial controllers and network equipment, where the requirement is to bring up a real-time operating system deterministically rather than to store a lot of data ^[1].

NAND cannot do this. Its first access to a page costs hundreds of times more than NOR's, and it is addressed in pages rather than bytes. The standard workaround is shadowing: copy the boot image out of NAND into RAM and execute from there, the same trick PCs have used to move BIOS into memory for decades ^[1]. Micron noted as early as 2006 that an increasing number of processors could boot directly from NAND without any NOR at all, and predicted XIP would cease to be a design consideration ^[1]. That prediction was partly right: NOR's addressable market shrank to embedded code storage and never recovered, but it did not vanish either.

The niche is not a museum piece. TrendForce forecast in July 2026 that SLC NAND contract prices would rise 120% to 170% in the second half of 2026 against the first half, because manufacturers were redirecting mature-process capacity toward high-layer-count 3D NAND, no major supplier planned new SLC capacity, and industrial, automotive and networking customers were migrating to 4 Gb and 8 Gb SLC parts for their reliability and 100,000 program/erase cycle endurance ^[11]. TrendForce lists AI and edge inference equipment among the drivers, on the grounds that such systems need fast, deterministic boot of a mission-critical real-time operating system, and data centers among them too, where SLC serves as boot media and as a write-intensive buffer ^[11].

Bits per cell

The cheapest way to add capacity without changing the process is to store more than one bit in each cell, by dividing the threshold-voltage window into more states. Two bits require 4 states, three require 8, four require 16, five require 32. The window does not get wider, so each added bit halves the voltage margin between adjacent states, and everything that perturbs a cell's threshold voltage (charge leakage, interference from neighbours, disturbance from nearby reads and programs) becomes proportionally more dangerous.

Scroll sideways for more →

The endurance collapse across the ladder is the headline number and the one most often garbled. Micron's SLC-era note put nominal block endurance at 100,000 program/erase cycles ^[1]. Cai and colleagues report that 5x-nm planar MLC could endure roughly 10,000 program/erase cycles per block, while 1x-nm MLC and TLC endured roughly 3,000 and roughly 1,000 respectively ^[2]. Those are planar-era figures, and the move to 3D relaxed the pressure by allowing a physically larger cell at a relaxed design rule, so modern 3D TLC does considerably better. The direction of the effect is what generalises: within any one process generation, each extra bit per cell costs endurance, costs retention, and costs latency, because more states mean finer ISPP steps to program and more sensing operations to read.

QLC is where the AI buildout has landed. TrendForce noted in June 2026 that multiple suppliers had expanded high-capacity QLC shipments during the enterprise SSD shortage, with SanDisk's QLC products entering volume shipment ^[9]. Kioxia's LC9 series, announced on 21 July 2025 in the Americas and 22 July 2025 by Kioxia Corporation and sampling to selected customers at the time, reaches 245.76 TB in a single 2.5-inch or E3.L drive by stacking 32 dies of 2 Tb eighth-generation BiCS QLC with CMOS-bonded-to-array packaging, and is aimed explicitly at storing training datasets for large language models and at embedding and vector database workloads ^[17].

PLC is the case where careful language matters. It has been discussed by every major vendor since roughly 2019 and none of them sells it. Blocks & Files summarised the position in January 2026: QLC 3D NAND is fabricated commercially, PLC is not, because a PLC cell's read reliability and endurance are both too low ^[16]. The most interesting recent attack on the problem is SK hynix's Multi-Site Cell work, presented at IEDM in December 2025, which splits each 3D NAND cell into two halves of six voltage states each rather than driving one cell to 32 states, and claims a 20-fold read speed improvement over conventional PLC and 25% more capacity than a QLC die ^[16]. SK hynix has built working wafers; it has not said it can manufacture them economically ^[16]. Treating that as a shipping PLC product would be wrong.

Below the ladder, planar NAND is being retired outright. Kioxia issued an end-of-life notice in April 2026 covering its 2D planar NAND at 15, 24 and 32 nm design rules in SLC, MLC and TLC formats along with 64-layer 3D parts, with sales ending after September 2026 and final shipments by the end of 2028; Micron and SK hynix had already abandoned planar NAND, and Samsung stopped 2D NAND manufacturing in March 2026 and converted the line to DRAM ^[15].

Why the industry went vertical

Planar NAND scaled by shrinking the cell, and it stopped at around 20 nm because the floating gate became too small to hold a statistically reliable number of electrons and because neighbouring floating gates coupled capacitively into each other. Both problems get worse with multi-level cells, since the voltage window between states is already narrow. Cai and colleagues frame the whole reliability problem of the era in exactly those terms: process scaling and multi-level coding together mean fewer electrons per cell and larger cell-to-cell interference and disturbance effects ^[2].

The escape was to stop shrinking laterally and start stacking vertically, and to replace the conductive floating gate with an insulating charge-trap layer that can run continuously up a vertical string without the trapped charge redistributing along it. What this bought was continued cost-per-bit reduction without lithography scaling, which is why NAND has stayed cheap through a decade in which leading-edge logic became ruinously expensive, and why a manufacturer without access to extreme ultraviolet tools can still compete in NAND. The structure, the etch that limits it, the string-stacking workaround, the wafer-bonded periphery and the layer race are all covered at 3D NAND. Two cautions from there apply to any figure quoted elsewhere: advertised layer counts include dummy layers that store nothing, and several vendors no longer publish a layer count at all, so the public numbers come from teardowns.

Endurance, disturbance and error correction

Raw NAND is not reliable enough to store data on its own. It is made reliable by the controller, and the distance between the raw bit error rate coming off the die and the error rate the host is allowed to see is very large. Four physical mechanisms drive the raw rate up, and all four get worse together.

Wear. Every program/erase cycle degrades the tunnel oxide. Repeated high-field stress traps charge in the oxide and creates defects, which lets electrons tunnel out more easily afterwards; the practical effect is that a heavily cycled block both leaks faster and programs less predictably ^[2]. A block is worn out when it can no longer hold data for the manufacturer's minimum retention period, not when it stops accepting writes ^[2].

Retention. Charge leaks away over time even with the drive powered off, shifting thresholds downward. Cai and colleagues measured threshold distributions on real 1x-nm MLC parts at one day, one month and one year of retention age and found both a downward shift and a widening of every state, the widening caused by charge detrapping ^[2]. Retention loss and wear compound: the more cycles a block has taken, the more trapped charge exists to detrap, and the faster it loses data ^[2].

Read disturb. Reading a cell requires driving every other cell on the string into a pass state with a voltage high enough to conduct regardless of stored charge. That pass voltage weakly programs the cells it is applied to. Cai and colleagues cycled a block, then read a single word line up to 100,000 times, and observed the threshold voltages of cells in the erased and lowest programmed states shifting upward ^[2]. Read-only data is therefore not safe data, and controllers count reads per block and rewrite blocks that pass a threshold.

Program interference. Programming one cell shifts the apparent threshold of its neighbours through capacitive coupling. This was the mechanism that ended planar scaling, and it is why program order within a block is fixed by the controller rather than chosen freely.

The industry standard that turns these mechanisms into a warranty is JEDEC JESD218, which defines endurance in terms of terabytes written under a specified workload, subject to holding a retention and an error-rate requirement at end of life. The requirements differ sharply by application class:

Scroll sideways for more →

Source: JEDEC JC-64.8 presentation of JESD218 requirements ^[7].

Two things in that table are routinely misreported. The retention figure is an end-of-life requirement for a fully worn drive at a stated temperature, not a shelf life for a healthy one, and enterprise drives have a shorter power-off retention requirement than client drives, not a longer one, because they are assumed to be running. JESD218 also spells out how a TBW rating is derived: endurance rating is bounded by drive capacity times the NAND's cycling capability, divided by the write amplification factor and by a guard band for uneven wear (the JEDEC worked example uses a factor of two, on the assumption that the most heavily cycled block takes twice the average) ^[7].

Error correction. Early SSDs used BCH codes, which correct up to a fixed number of bit errors per codeword using hard decisions: the controller reads the page, the decoder either succeeds or fails, and on failure the controller retries the read at shifted reference voltages and tries again ^[2]. As cells got noisier this stopped being enough, and the industry moved to low-density parity-check (LDPC) codes. The important difference is not raw correction strength but that LDPC fails gracefully. Its decoder consumes soft information, a likelihood for each bit rather than a decision, and the controller can generate that information by reading the same page several times at slightly different reference voltages ^[2]. So an LDPC drive degrades through a ladder: hard decoding first, then progressively more expensive levels of soft decoding, then drive-level parity recovery. The cost is latency, and it is not small. Cai and colleagues note that a five-level soft decoding step can require up to 480 microseconds ^[2]. This is the mechanism behind a familiar symptom: an old, heavily written drive that still returns correct data but has become erratically slow, because a growing fraction of its reads are climbing the decoding ladder.

The controller and the flash translation layer

A NAND die cannot be used as a block device directly, because block devices allow arbitrary in-place overwrites and NAND does not. The bridge is the flash translation layer (FTL), firmware running on the drive controller.

The FTL maintains a mapping from the logical addresses the host uses to the physical pages where data actually lives ^[2]. When the host overwrites a logical address, the FTL does not erase anything. It writes the new data to a page in whichever block is currently open for writes, updates the mapping, and marks the old physical page invalid ^[2]. Over time blocks fill with invalid pages, and the FTL runs garbage collection: pick a fragmented block, copy its remaining valid pages elsewhere, erase it, return it to the free list ^[2]. Selection normally favours the block with the fewest valid pages, since that minimises the copying.

This creates write amplification: the flash sees more bytes written than the host sent, because garbage collection and refresh operations move data the host never touched ^[2]. Write amplification is the single most important number in SSD endurance, because a drive's usable lifetime is its NAND's cycle budget divided by its write amplification factor.

Over-provisioning is the lever that controls it. Manufacturers fit more physical flash than they expose to the operating system; the hidden remainder keeps the free list full, which means garbage collection can wait longer before it has to reclaim a block, which means the blocks it eventually picks contain fewer valid pages to copy ^[2]. The relationship is non-linear and strongly favourable at the low end: with generous over-provisioning, write amplification approaches 1 ^[2]. That is why an enterprise drive rated for several drive-writes per day and a consumer drive built from the same dies can differ by a factor of several in endurance while being physically almost identical, and it is also why deliberately leaving a partition unallocated on a consumer SSD measurably improves its sustained write behaviour.

Over-provisioning also trades directly against error correction, because parity bits live in the same spare space. Cai and colleagues set out the trade explicitly: a stronger code tolerates a higher raw bit error rate and therefore more program/erase cycles, but consumes space that would otherwise reduce write amplification ^[2].

TRIM exists because of the same asymmetry. When a file is deleted, the file system stops referring to those logical addresses, but without being told, the FTL still believes the corresponding physical pages hold valid data and will faithfully copy them during garbage collection. The TRIM command (UNMAP in SCSI, Dataset Management Deallocate in NVMe) lets the host declare a range dead so the FTL can drop it from the mapping and skip it. A drive whose host never issues TRIM slowly fills with garbage it is obliged to preserve, and its write amplification climbs.

Wear levelling distributes cycles so that no block wears out far ahead of the rest, by periodically moving static data out of lightly cycled blocks so those blocks re-enter circulation ^[2]. Bad block management retires blocks that fail, which is expected behaviour rather than a defect: NAND ships with factory-marked bad blocks and accumulates more in service, and Micron's note treats ECC and bad-block management as mandatory parts of any NAND design ^[1].

Two consequences are worth stating plainly. First, SSD performance is a controller property at least as much as a media property. Sequential read throughput mostly tracks the interface and the number of channels, but sustained random write, latency under mixed load, and behaviour on a full drive are functions of FTL design, mapping granularity, DRAM buffer size, SLC-cache policy and garbage collection scheduling. Two drives with identical NAND and different controllers are not the same product. Second, the indirection makes secure deletion genuinely hard: a host-level delete or overwrite does not reach the physical pages, and a study of commercial NAND media at IIT Delhi and DRDO recovered 100% of data after ordinary Windows and Linux delete and erase commands, with wear levelling and bad-block management named as contributors to the problem ^[5].

Interfaces, packaging and form factors

A NAND package contains one or more dies; a die contains planes that can carry out operations in parallel; a plane contains blocks; a block contains pages. A drive controller talks to several packages over independent channels, and nearly all of an SSD's throughput is bought by issuing operations concurrently across channels, dies and planes rather than by any one die being fast. A single page program is slow in absolute terms; a drive delivering gigabytes per second is running a great many of them at once. Micron's note makes the packaging point directly: the same interface and package can carry a single die or several stacked ones, so density scales without a board redesign ^[1].

The raw NAND interface itself is a parallel bus shared by the dies on a channel. Two standards compete. The Open NAND Flash Interface (ONFI) was formed in 2006 by a group including Intel, Micron, SK Hynix, SanDisk, Phison and Sony, and publishes open specifications; Toggle DDR came from Samsung and Toshiba and evolved through customer-specific device specifications rather than public releases ^[6]. The technical divergence is mostly about clocking: ONFI moved from asynchronous transfer to a source-synchronous scheme with a clock and a data strobe from version 2.0, while Toggle transfers on both edges of a strobe without a free-running clock ^[6]. Both have converged on very similar data rates, in the region of 2400 MT/s and above at the 5.0 generation of each ^[6].

Above the raw interface sit the drive protocols, and this is where the largest single jump in SSD performance came from. SATA Revision 3.0, launched in 2009, transfers at 6 Gb/s, roughly 600 MB/s, and carries AHCI, an instruction set originally developed for hard drives; Kioxia's comparison of server SSD interfaces notes that a SATA SSD's commands "must traverse through a software stack that was not designed for flash-based SSDs," and that SATA offers a queue depth of 32 in a single command queue ^[20]. NVM Express was designed from the ground up for flash and uses PCI Express as its transport, supporting a queue depth of 64K commands across 64K queues and bypassing the host bus adapter entirely ^[20]. Bandwidth scales with PCIe lanes and generations: Kioxia puts a PCIe Gen4 lane at up to 2 GB/s, so a x4 drive reaches roughly 8 GB/s ^[20], and the Gen5 LC9 quotes a maximum of 128 GT/s over a single x4 or dual x2 link under NVMe 2.0 ^[17].

Form factors have specialised around thermal and density limits rather than around the media:

Scroll sideways for more →

The EDSFF family (Enterprise and Data Center Standard Form Factor) exists because M.2 cannot dissipate the power a modern controller needs and 2.5-inch bays waste volume, and because a rack of AI servers wants many drives that can be serviced without downtime.

Market structure

NAND is an oligopoly, though a less concentrated one than DRAM. TrendForce's revenue tracking for the first quarter of 2026 gives the shape:

Scroll sideways for more →

Source: TrendForce, 25 May 2026 ^[8]. Shares are of TrendForce's supplier total and are not directly comparable with another analyst's definition of the whole market.

The corporate structure behind that table is unusually tangled. Solidigm is the former Intel NAND and SSD business, which Intel sold to SK hynix ^[19], and TrendForce counts it inside the SK hynix group ^[8]. SanDisk is the former Western Digital flash business: Western Digital separated its flash unit into an independent Sandisk Corporation in February 2025, announcing completion on 24 February and keeping the hard disk business for itself ^[21]. Sandisk and Kioxia run joint-venture fabs and share the output, which is why the two sample and ship the same BiCS generations ^[22]. YMTC, the sixth significant producer, does not appear in TrendForce's top-five revenue table because much of its output leaves the fab as wafers and packaged dies bound for Chinese module makers rather than as branded product; its position is normally expressed as a share of wafer capacity or bit output instead. YMTC is also the clearest illustration of why NAND is the leading-edge memory a sanctioned manufacturer can still advance, since density comes from stacking rather than from lithography. See China's semiconductor industry and AI chip export controls.

The 2025-2026 shortage

Through 2025 and 2026 NAND went from oversupply to acute shortage, and the mechanism was allocation rather than a production failure. AI data center operators wanted very large quantities of high-capacity enterprise SSDs; suppliers, facing a fixed wafer base, moved capacity toward the products with the best margins; and everything downstream of that decision got squeezed.

The enterprise numbers are extreme. TrendForce reported enterprise SSD revenue at the top five brands reaching 18.46 billion dollars in the first quarter of 2026, up 86.1% quarter on quarter, with contract prices up roughly 80% in the quarter, supplier inventories at historic lows, and output lagging orders ^[9]. Samsung alone took 7.05 billion dollars of that, up 92.8% ^[9]. TrendForce attributed the demand specifically to the rapid adoption of AI agent services and to cloud service provider procurement, and described suppliers repositioning SSDs as components that support computation rather than merely store data ^[9].

The consumer side absorbed the cost. TrendForce reported in December 2025, citing Commercial Times, that PC and notebook OEMs were planning to cut standard SSD configurations, 512 GB models down to 256 GB and 1 TB down to 512 GB, to hold device prices; that module makers had inventory lasting only into the first quarter of 2026 with some running out as early as March; and that Micron's NAND spot quotes had jumped nearly 50% in a single month ^[13]. The most direct corporate response came from Micron, which announced in early December 2025 that it would exit the Crucial consumer brand entirely and end retail and distribution sales of Crucial memory and storage worldwide by February 2026, with executive vice president Sumit Sadana attributing the decision to surging demand for memory and storage in the AI-driven data center market ^[18]. A supplier walking away from the entire consumer channel to serve data centers is the clearest single signal of where NAND was being allocated.

By mid-2026 the rate of increase was moderating without the level coming down. TrendForce projected overall NAND contract prices up 10% to 15% quarter on quarter in the third quarter of 2026, much slower than preceding quarters, with client SSD and NAND wafer increases moderating substantially because OEM inventories were high and module makers could not pass costs through, while enterprise SSD prices continued upward on capacity reallocation toward AI and server products ^[10].

A second-order effect made the squeeze worse. Nearline hard drives went short at the same time. TrendForce reported in September 2025 that nearline HDD lead times had gone from a few weeks to over 52 weeks because HDD makers had not expanded capacity for years, and that the shortage was pushing cold-data demand toward high-capacity QLC SSDs, which also draw about 30% less power than nearline HDDs ^[12]. That pushed even more demand onto NAND at exactly the wrong moment.

The cost gap that resulted is worth quoting carefully, because it comes from an interested party. VDURA, which sells mixed HDD-and-flash systems and therefore benefits from the comparison, published a Flash Volatility Index putting 30 TB of QLC SSD capacity at 4.9 times the cost of 30 TB of HDD capacity in the second quarter of 2025 and 22.6 times in the first quarter of 2026, with the absolute price of a 30 TB QLC SSD rising from 2,450 dollars to 15,121 dollars over those nine months ^[14]. Blocks & Files, reporting the figures, flagged VDURA's commercial interest explicitly ^[14]. The direction is corroborated by the contract-price data above; the exact multiple should be treated as a vendor's index rather than a market price.

Alternatives and failed successors

Hard disks remain far cheaper per bit and are not going away for cold data, which is the entire content of the cost comparison above. Their disadvantages are latency, random-access throughput and power, and their supply is currently as constrained as NAND's ^[12][14]. The practical outcome in AI data centers has been tiering rather than replacement: flash for anything in the training or serving path, disk for archives and for data that is written once and read rarely.

Storage-class memory, the category of non-volatile devices meant to sit between DRAM and NAND, mostly failed commercially. The most prominent attempt was 3D XPoint, developed jointly by Intel and Micron and sold by Intel as Optane. Micron withdrew from 3D XPoint manufacturing in March 2021 and later sold the Lehi fab, leaving Intel without a producer ^[19]. Intel wound the business down the following year: Blocks & Files reported on 29 July 2022 that chief executive Pat Gelsinger had announced Intel was "making the difficult decision to wind down our efforts in Optane as we embrace CXL, a standard which Intel Corporation pioneered" ^[19]. The technology worked and was genuinely faster than NAND with far better endurance. It failed on cost per bit against a NAND industry that kept adding layers, and on the absence of a second source. Compute Express Link, which lets a host attach memory over PCIe, absorbed much of the use case that Optane persistent memory was meant to fill.

DRAM is not an alternative to NAND but its complement, and the two are worth contrasting because the AI shortage hit both at once. DRAM is volatile, byte-addressable, roughly a thousand times lower in latency, and orders of magnitude more expensive per bit; NAND is non-volatile, page-addressed, and cheap. The AI memory hierarchy runs SRAM on the accelerator die, High Bandwidth Memory beside it, DRAM on the host, and NAND underneath. The volatile side of that stack went through its own 2025-2026 squeeze, with the same underlying cause: capacity reallocated toward whatever AI data centers were willing to pay most for.

NAND in AI infrastructure

The workloads that put NAND on the critical path of an AI cluster are less glamorous than the AI accelerator but no less necessary.

Training corpora and dataset shards are read repeatedly and at very high aggregate bandwidth; a data pipeline that cannot keep an accelerator fleet fed wastes the most expensive hardware in the building. Checkpoints are the opposite pattern: enormous, bursty, latency-insensitive writes, repeated often enough that checkpoint write bandwidth becomes a scheduling parameter on large training runs. Serving adds two more. Vector indexes for retrieval have outgrown host memory on many deployments and are increasingly served partly from flash. And the KV cache of a long-context inference system is a natural candidate for spilling to fast local NVMe when it will not fit in HBM, since recomputing attention state is expensive and rereading it from a local SSD may not be.

Vendors have responded by building drives specifically for this shape of demand. Kioxia positioned the 245.76 TB LC9 at exactly these workloads: storing datasets for training large language models, creating embeddings, and backing vector databases and data lakes ^[17]. TrendForce's framing of the enterprise SSD surge is the same, describing suppliers moving SSDs from a storage role to one supporting computational workloads inside AI systems ^[9].

The commercial coupling runs the other way too, and it is the part most often missed. Because NAND capacity is fungible between a hyperscaler's enterprise SSD order and a laptop's boot drive, and because the hyperscaler can absorb a far higher price per gigabyte, AI demand sets the price of consumer storage. The 2026 evidence for that is a supplier abandoning the retail channel ^[18], OEMs halving the storage in shipping laptops ^[13], and enterprise contract prices rising 80% in a quarter ^[9].

See also

• 3D NAND
• DRAM
• SRAM
• High Bandwidth Memory
• Kioxia
• YMTC
• SK hynix
• Micron Technology
• Data center
• AI accelerator

References

1. ^Micron Technology, "TN-29-19: NAND Flash 101, An Introduction to NAND Flash and How to Design It In to Your Next Product," rev. B, April 2010 (originally 2006). user.eng.umd.edu/...micron-tn2919.pdf
2. ^Yu Cai, Saugata Ghose, Erich F. Haratsch, Yixin Luo and Onur Mutlu, "Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives," Proceedings of the IEEE, vol. 105, no. 9, pp. 1666-1704, 2017. arxiv.org/...1706.08642
3. ^Kioxia, "Where is Memory Technology From, and Where is it Headed," October 2019. kioxia.com/...history-of-our-memory-201910
4. ^Kioxia America, "35th Anniversary of the Invention of NAND Flash." americas.kioxia.com/...flash35
5. ^Abhilash Garg, Supriya Chakraborty, Manoj Malik, Devesh Kumar, Satyajeet Singh and Manan Suri, "Investigation of Data Deletion Vulnerabilities in NAND Flash Memory Based Storage," arXiv:2001.07424, 21 January 2020. arxiv.org/...2001.07424
6. ^Phison, "NAND Flash 101: Flash Device Interfaces." phisonblog.com/...sh-101-flash-device-interfaces-2
7. ^Alvin Cox (Seagate), chairman JC-64.8, "JEDEC SSD Specifications Explained," JEDEC. jedec.org/...ox%20%5BCompatibility%20Mode%5D_0.pdf
8. ^TrendForce, "Combined Revenue of Top Five Global NAND Flash Suppliers Rose by 83.7% QoQ for 1Q26 as Supply Shortages Drove Price Hikes," 25 May 2026. trendforce.com/...20260525-13058
9. ^TrendForce, "AI Agent Boom Triggers Enterprise SSD Supply Crunch; Top Five Enterprise SSD Brands Post Record US$18.46 Billion Revenue in 1Q26," 11 June 2026. trendforce.com/...20260611-13092
10. ^TrendForce, "AI Server Demand Continues to Support Memory Prices in 3Q26, but Gains Moderate as Consumer Demand Weakens and High Base Effects Take Hold," 3 July 2026. trendforce.com/...20260703-13134
11. ^TrendForce, "Niche Demand and MLC Migration to Drive SLC NAND Prices up 120-170% in 2H26," 13 July 2026. trendforce.com/...20260713-13142
12. ^TrendForce, "Soaring Inference AI Demand Triggers Severe Nearline HDD Shortages; QLC SSD Shipments Poised for Breakout in 2026," 15 September 2025. trendforce.com/...20250915-12714
13. ^TrendForce, "NAND Flash 'Dry Year' Looms as Stock-Out Risk Reportedly Forces PC OEMs to Cut SSD Specs," 10 December 2025. trendforce.com/...-forces-pc-oems-to-cut-ssd-specs
14. ^Chris Mellor, "VDURA says 30 TB QLC SSD capacity now costs 22.6x more than HDD," Blocks & Files, 8 April 2026. blocksandfiles.com/...5214761
15. ^Chris Mellor, "Kioxia killing off old NAND chippery," Blocks & Files, 2 April 2026. blocksandfiles.com/...5214219
16. ^Chris Mellor, "SK hynix developing split-cell 5-bit flash," Blocks & Files, 15 January 2026. blocksandfiles.com/...4090388
17. ^Kioxia America, "KIOXIA Announces Industry's First 245.76 TB NVMe SSD Built for the Demands of Generative AI Environments," 21 July 2025. americas.kioxia.com/...ssd-20250721-1
18. ^Tom Coughlin, "Micron Exits Consumer Business And Focuses On AI And Data Center Sales," Forbes, 7 December 2025. forbes.com/...-focuses-on-ai-and-data-center-sales
19. ^Chris Mellor, "Intel at 3D exit point: Alas poor Optane, I knew it well," Blocks & Files, 29 July 2022. blocksandfiles.com/...s-poor-optane-i-knew-it-well
20. ^Kioxia America, "Comparing SSD Interfaces in Servers," best practices brief. americas.kioxia.com/..._Servers_Best_Practices.pdf
21. ^Western Digital, "Western Digital Completes Planned Company Separation," 24 February 2025. westerndigital.com/...s-planned-company-separation
22. ^Chris Mellor, "Kioxia and Sandisk sample shipping 332-layer 3D NAND," Blocks & Files, 3 July 2026. blocksandfiles.com/...5266362