NVLink Fusion
NVLink Fusion is a program and silicon technology from NVIDIA that opens its NVLink high speed interconnect to third party chips. It lets partners connect their own CPUs and custom accelerators to NVIDIA GPUs, or attach their own accelerators to NVIDIA CPUs, so they can build semi custom rack-scale AI systems that still plug into NVIDIA's interconnect fabric. NVIDIA introduced it at Computex in Taipei on May 18, 2025, framing it as a way for the wider industry to build specialized AI infrastructure around NVLink rather than only buying complete NVIDIA systems. [1][2][9]
Since launch the program has widened from an interconnect licence into a rack-scale platform. NVIDIA now describes NVLink Fusion as bundling the NVLink scale-up fabric, an NVLink Fusion chiplet, the NVLink-C2C chip-to-chip link, a custom high-bandwidth memory technology called NVHBM, and the NVIDIA MGX rack architecture together with the supply chain behind it. [15][16] Named adopters as of September 2026 include Amazon Web Services, which is designing Trainium4 to integrate with NVLink 6 and MGX, and the inference chip startup d-Matrix, which will connect its Raptor XPUs to NVIDIA racks. [17][18]
The announcement matters because NVLink had been closed. For years it worked only between NVIDIA's own GPUs and, through a related link, between NVIDIA GPUs and NVIDIA's Grace CPUs. NVLink Fusion changes that by selling the interconnect as licensable building blocks. Partners can drop NVLink into their silicon and join racks that NVIDIA also populates. The move arrived as cloud providers design more of their own chips and as a competing open standard, UALink, gathered backing from several of NVIDIA's largest rivals. [3][4]
What NVLink Fusion is
NVLink is NVIDIA's scale up fabric, the wiring that ties many accelerators together inside a server or a rack so they behave more like one large machine. The fifth generation used in Blackwell systems delivers up to 1.8 terabytes per second of bidirectional bandwidth per GPU, which NVIDIA describes as roughly 14 times the bandwidth of a PCIe Gen5 link. [10] That gap is the reason NVLink exists. Large model training and high throughput inference move enormous amounts of data between chips, and a standard PCIe connection becomes a bottleneck. [2][5]
NVLink Fusion takes that same fabric and packages it so non NVIDIA silicon can join. NVIDIA offers it in two delivery forms. A partner can integrate NVLink interface IP directly into a chip design, or it can place an NVIDIA built NVLink chiplet next to its silicon in the same package. Either way the resulting part can speak NVLink to NVIDIA hardware across the rack. The word semi custom is the key idea. The customer brings custom silicon, and NVIDIA supplies the connective tissue plus at least one class of its own chips in the system. [3][5]
The generation now sold with the program is the sixth. NVIDIA's NVLink Fusion product page, as of September 2026, states that NVLink 6 and the NVLink Switch chip connect 72 accelerators all-to-all at 3.6 terabytes per second per accelerator, for 260 terabytes per second of aggregate bandwidth in a single NVL72 domain, with roadmap configurations reaching domain sizes of up to 1,152. [2] The switch supports peer-to-peer memory access through direct loads, stores and atomic operations, and runs NVIDIA's SHARP protocol for in-network reductions and multicast. [17]
What the program provides
By 2026 NVIDIA described NVLink Fusion as a set of components rather than a single licence. An August 2026 NVIDIA post lists them as NVLink chiplets, NVLink-C2C, NVLink switches, and NVIDIA MGX systems and racks, alongside the partner ecosystem of CPU designers, ASIC houses, system manufacturers and technology providers. [16]
| Component | What it does |
|---|---|
| NVLink Fusion chiplet | Dropped into a partner's package so a custom XPU can join the NVLink scale-up interconnect and NVLink Switch [17] |
| NVLink-C2C | Chip-to-chip link used to attach a partner CPU to NVIDIA GPUs, or a partner XPU to NVIDIA CPUs. NVIDIA says it delivers up to 6 times the energy efficiency of a PCIe interface [15] |
| NVLink Switch | The switched rack fabric that turns 72 accelerators into one scale-up domain [2][17] |
| NVHBM | A high-bandwidth memory technology announced August 26, 2026 that moves NVIDIA's memory controller into the HBM base die [16] |
| MGX rack architecture | The rack, tray, power and cooling standard, and the supplier ecosystem behind it [15][16] |
NVIDIA states that NVLink Fusion is CPU architecture agnostic and supports Arm, x86 and RISC-V processors, which partners attach using NVLink-C2C. [18]
NVHBM is the newest addition. NVIDIA says that by integrating its custom memory controller into the 3D HBM stack instead of the XPU die, NVHBM delivers up to 30 percent greater memory bandwidth and 15 percent lower HBM power consumption, and frees up to 25 percent more area on the XPU compute die, compared with standard HBM4E. Amazon's Annapurna Labs is the first partner working on it. [16]
How it extends NVLink to other silicon
NVLink Fusion supports two configurations, pointed in opposite directions.
The first path connects a partner's custom CPU to NVIDIA GPUs. Here the partner integrates NVLink chip to chip IP, the same family of technology NVIDIA calls NVLink-C2C, into its processor. NVLink-C2C is the short reach link NVIDIA already uses to bind its Grace CPU to its GPUs at high bandwidth. By licensing that interface, a company can build a CPU that sits next to NVIDIA GPUs and feeds them as tightly as NVIDIA's own Grace part would. Fujitsu and Qualcomm were the CPU partners named at the May 2025 launch, each pairing custom processors with NVIDIA GPUs. [1][6]
The second path runs the other way. A hyperscaler or chip designer builds a custom accelerator, often called an XPU or an ASIC, and places an NVLink chiplet beside it. That chiplet lets the accelerator plug into NVIDIA's NVLink rack fabric, the same switched network used in systems like the GB200 NVL72, so the custom part can scale up alongside or in place of NVIDIA GPUs. Custom silicon firms such as Marvell, MediaTek, and Alchip support this direction. [2][3]
In both cases the racks can keep using NVIDIA's networking for the scale out side, the links between racks and across the data center. That includes Spectrum-X Ethernet and ConnectX network interface cards, which gives partners a path to grow an AI factory to very large GPU counts while reusing NVIDIA's end to end stack. [1][2]
The partner ecosystem
NVIDIA grouped its launch partners by what they contribute. Custom silicon designers build the chips. Two firms supply CPUs that link to NVIDIA GPUs. Electronic design automation vendors, the companies whose tools engineers use to design chips, provide the IP and the flows that make integrating NVLink practical. A connectivity specialist supplies the physical fabric components.
| Partner | Role in NVLink Fusion |
|---|---|
| MediaTek | Custom silicon design for accelerators that scale up over NVLink |
| Marvell | Custom silicon and ASIC design for NVLink connected accelerators |
| Alchip Technologies | Custom ASIC design services for NVLink Fusion silicon |
| Astera Labs | Connectivity components and fabric silicon for NVLink Fusion systems |
| Cadence | EDA tools and IP for integrating NVLink interfaces into chip designs |
| Synopsys | EDA tools and IP for integrating NVLink interfaces into chip designs |
| Fujitsu | Custom CPUs that connect to NVIDIA GPUs over NVLink |
| Qualcomm Technologies | Custom CPUs that connect to NVIDIA GPUs over NVLink |
The mix is deliberate. None of these companies sells a data center GPU that competes head to head with NVIDIA. The CPU partners extend NVIDIA's reach into processors. The design service and EDA firms help customers build accelerators that still need NVIDIA's fabric to scale. So NVIDIA opens the door to custom silicon while keeping its GPUs central to the rack. [1][3][7]
The roster has changed since. NVIDIA's NVLink Fusion page, as of September 2026, sorts the ecosystem into four groups.
Qualcomm, named as a CPU partner at launch, does not appear on NVIDIA's ecosystem page as of September 2026. NVIDIA has not announced a withdrawal, and the only evidence is the name's absence from the current listing.[1][2]
NVIDIA separately names AWS and d-Matrix as adopters, that is, companies putting their own silicon into NVLink Fusion racks rather than supplying design services to others. [18]
Adoption timeline
| Date | Development |
|---|---|
| May 18, 2025 | NVLink Fusion announced at Computex with MediaTek, Marvell, Alchip, Astera Labs, Cadence, Synopsys, Fujitsu and Qualcomm [1] |
| September 18, 2025 | Intel agreed to build NVIDIA-custom x86 CPUs that connect to NVIDIA infrastructure over NVLink, alongside a $5 billion NVIDIA investment in Intel common stock at $23.28 per share [11] |
| October 13, 2025 | At the OCP Global Summit NVIDIA said Intel and Samsung Foundry were joining the NVLink Fusion ecosystem [12] |
| December 2, 2025 | At AWS re:Invent, Amazon Web Services said it is designing Trainium4 to integrate with NVLink 6 and the MGX rack architecture, the first step of a multi-generational collaboration [13][17] |
| March 31, 2026 | Marvell entered a strategic partnership to supply custom XPUs and NVLink Fusion compatible scale-up networking, with NVIDIA investing $2 billion in Marvell [14] |
| August 26, 2026 | NVIDIA expanded NVLink Fusion with NVHBM; Amazon's Annapurna Labs named as the first memory collaborator [16] |
| August 31, 2026 | MediaTek said it would adopt the NVLink Fusion platform as a design foundation for customer XPUs, with NVIDIA investing $3.5 billion in MediaTek convertible bonds [19] |
| September 10, 2026 | d-Matrix announced it will integrate Raptor inference XPUs into an MGX rack through NVLink Fusion, with initial availability expected in Q4 2027 [18][20] |
The d-Matrix agreement
The September 2026 d-Matrix announcement is the clearest public description of what an NVLink Fusion deployment looks like. d-Matrix said it would place its next-generation Raptor XPUs, a follow-on to the Corsair platform, directly into an NVIDIA rack reference design built from Vera CPUs, NVLink switches, BlueField-4 DPUs, ConnectX-9 SuperNICs and Spectrum-X Ethernet, in modular cable-free trays drawn from the MGX ecosystem and supply chain. Astera Labs supplies connectivity for the system. Raptor was expected to tape out before the end of 2026, and initial availability of Raptor XPUs in an MGX rack is expected in the fourth quarter of 2027. [20]
The intended usage pattern is heterogeneous disaggregation: splitting an inference request so that NVIDIA GPUs handle the compute-heavy prefill phase while d-Matrix XPUs handle the latency-sensitive decode phase, inside one rack architecture. [20]
Jensen Huang framed the deal in terms of accelerator choice. "NVLink Fusion enables partners to integrate custom silicon with NVIDIA's deep ecosystem of NVLink, advanced packaging, rack-scale systems and networking technologies," he said. [20]
Strategic rationale
NVLink Fusion is a shift in how NVIDIA sells. The traditional model was to ship complete chips and complete systems. NVLink Fusion adds a licensing model layered on top, where NVIDIA earns from the interconnect and the surrounding platform even when a customer builds part of the silicon itself. [4][7]
The timing tracks the rise of custom accelerators. The largest cloud companies have been designing their own AI chips to cut cost and reduce dependence on any single vendor. Left unaddressed, that trend would route spending away from NVIDIA. NVLink Fusion offers those customers a middle path. They can deploy custom parts and still buy into NVIDIA's rack architecture, its networking, and its software. As Jensen Huang, NVIDIA's founder and chief executive, put it at launch, "NVLink Fusion opens NVIDIA's AI platform and rich ecosystem for partners to build specialized AI infrastructures." [1]
Several of the later partnerships came with capital attached. NVIDIA invested $5 billion in Intel common stock in September 2025, $2 billion in Marvell in March 2026, and $3.5 billion in MediaTek convertible bonds in August 2026, in each case alongside an NVLink Fusion commitment. [11][14][19]
NVIDIA's own argument for the program is that building a custom accelerator is the easy part. An August 2026 post lists what follows: integrating high-speed CPU and scale-up interfaces, sourcing and validating a scale-up network, designing compute and switch trays, designing and validating a rack including cooling and power, integrating security and storage, and managing the supplier ecosystem. NVLink Fusion sells the answer to all of those as a package. [15]
The competitive backdrop is UALink. The Ultra Accelerator Link effort is an open, consortium governed standard for connecting accelerators at scale, backed by AMD, Broadcom, Intel, Google, Microsoft, Meta, and others. Its pitch is an accelerator to accelerator fabric that needs no NVIDIA component. NVLink Fusion is widely read as NVIDIA's answer. Where UALink asks the industry to standardize around a neutral spec, NVIDIA offers its own mature fabric on licensable terms and keeps itself in the loop. [3][4][8]
Relationship to NVLink, NVLink-C2C, and Grace and Blackwell systems
NVLink Fusion does not replace NVLink. It is the same fabric, repackaged for outside silicon. Inside NVIDIA's own products NVLink keeps doing what it always did, tying GPUs together and, through NVLink-C2C, tying the Grace CPU to NVIDIA GPUs. NVLink Fusion exposes those interfaces so partners can build the same kinds of connections from their side. [2][5]
The reference point is the rack scale systems NVIDIA already ships. A GB200 NVL72 connects 72 Blackwell GPUs into a single NVLink domain through NVLink switches, so the whole rack acts like one accelerator for a large job. NVLink Fusion lets a partner's custom CPU or custom accelerator participate in that style of domain rather than sit outside it on a slower link. The follow on architectures NVIDIA has outlined, including Vera Rubin, continue the same scale up approach, which gives NVLink Fusion a long runway. [2][5]
That continuity is now explicit. NVIDIA says NVLink Fusion is offered with each generation of its rack-scale system architecture, and that XPU-based and GPU-based systems such as Vera Rubin NVL72 can share rack footprints, networking, cooling, power delivery and management, so an operator can start a data center buildout before deciding the final silicon mix. [15][16]
Significance and criticism
For NVIDIA the program is a hedge. If custom silicon keeps growing, NVLink Fusion captures some of that spending through interconnect licensing, networking, and rack design instead of losing it outright. For partners it lowers the bar to building competitive rack scale systems, since they can lean on a proven fabric rather than invent one. [4][7]
The main criticism at launch was that it is not truly open. Every NVLink Fusion configuration announced in May 2025 still required NVIDIA silicon at its center, a GPU or a CPU, and NVIDIA controls the specification. If you brought a custom CPU you connected it to NVIDIA GPUs, and if you brought a custom accelerator you connected it to an NVIDIA CPU. Customers could add their own chips, but only inside a system that remained tethered to NVIDIA's platform. Reporters and analysts contrasted this with UALink, which needs no NVIDIA part and is governed by a neutral body. The reading was that NVLink Fusion lets NVIDIA look open while preserving its lock in. [3][4][8]
NVIDIA's 2026 material describes the terms more loosely. It says adopters "can use as little or much of the platform as they want" and can "optionally incorporate" NVIDIA Rubin GPUs, Vera CPUs, co-packaged optics switches, ConnectX SuperNICs, BlueField DPUs and full-rack solutions. [15][17] The commercial pull is the ecosystem rather than a hard technical requirement: the fabric, the rack and the supply chain are NVIDIA's, and the specification remains NVIDIA's to set.
The launch partner list also reinforced the lock-in reading, since the most direct GPU rivals were absent. That has partly changed: Intel, a UALink backer, joined the NVLink Fusion ecosystem in 2025 and now appears on NVIDIA's CPU partner list, though it joined as an x86 CPU supplier rather than as an accelerator vendor. AMD and Broadcom remain outside the program. [3][8][11][12]
Limitations
NVLink Fusion is delivered as IP, chiplets and rack designs that partners must design into silicon and systems, which means adoption shows up only as those custom parts tape out and ship. That lag is long: AWS committed in December 2025 for Trainium4, and d-Matrix's announced availability for Raptor in an MGX rack is the fourth quarter of 2027. [17][20]
NVIDIA has not published licensing terms, royalties or pricing for the program, and the announcements describe partnerships and technical scope rather than commercial conditions. Several technical specifics beyond the headline bandwidth figures and the delivery forms were left for later disclosure. [1][3][5]
References
- ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8NVIDIA. "NVIDIA Unveils NVLink Fusion for Industry to Build Semi-Custom AI Infrastructure With NVIDIA Partner Ecosystem." NVIDIA Newsroom, May 18, 2025. nvidianews.nvidia.com/...ructure-partner-ecosystem
- ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8 ^9 ^10 ^11 ^12 ^13NVIDIA. "NVLink Fusion." NVIDIA data center product page, accessed September 15, 2026. nvidia.com/...nvlink-fusion
- ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8SiliconANGLE. "At Computex, Nvidia debuts AI GPU compute marketplace, NVLink Fusion and the future of humanoid AI." May 19, 2025. siliconangle.com/...link-fusion-future-humanoid-ai
- ^1 ^2 ^3 ^4 ^5The Register. "Nvidia opens NVLink to rivals." May 19, 2025. theregister.com/...nvidia_nvlink_fusion
- ^1 ^2 ^3 ^4 ^5Tom's Hardware. "Nvidia announces NVLink Fusion to allow custom CPUs and AI Accelerators to work with its products." May 19, 2025. tomshardware.com/...tors-to-work-with-its-products
- ^NVIDIA Investor Relations. "NVIDIA Unveils NVLink Fusion for Industry to Build Semi-Custom AI Infrastructure With NVIDIA Partner Ecosystem." May 18, 2025. investor.nvidia.com/...default
- ^1 ^2 ^3AI Magazine. "The AI Round up of Nvidia's Announcements at Computex." May 2025. aimagazine.com/...vidias-announcements-at-computex
- ^1 ^2 ^3EfficientlyConnected. "NVLink Fusion vs UALink: The Battle for AI Interconnect." 2025. efficientlyconnected.com/nvlink-fusion-vs-ualink
- ^StorageNewsletter. "Computex 2025: NVIDIA Unveils NVLink Fusion." May 19, 2025. storagenewsletter.com/...dia-unveils-nvlink-fusion
- ^Neowin. "Nvidia announces new NVLink Fusion that delivers 14x the bandwidth of PCIe Gen5." May 2025. neowin.net/...ivers-14x-the-bandwidth-of-pcie-gen5
- ^1 ^2 ^3NVIDIA. "NVIDIA and Intel to Develop AI Infrastructure and Personal Computing Products." NVIDIA Newsroom, September 18, 2025. nvidianews.nvidia.com/...rsonal-computing-products
- ^1 ^2NVIDIA. "NVIDIA, Partners Drive Next-Gen Efficient Gigawatt AI Factories in Buildup for Vera Rubin." NVIDIA Blog, October 13, 2025. blogs.nvidia.com/...tt-ai-factories-ocp-vera-rubin
- ^NVIDIA. "NVIDIA and AWS Expand Full-Stack Partnership, Providing the Secure, High-Performance Compute Platform Vital for Future Innovation." NVIDIA Blog, December 2, 2025. blogs.nvidia.com/...partnership-expansion-reinvent
- ^1 ^2NVIDIA. "NVIDIA AI Ecosystem Expands as Marvell Joins Forces Through NVLink Fusion." NVIDIA Newsroom, March 31, 2026. nvidianews.nvidia.com/...ces-through-nvlink-fusion
- ^1 ^2 ^3 ^4 ^5 ^6NVIDIA. "How XPUs Meet a World-Class AI Factory." NVIDIA Blog, August 24, 2026. blogs.nvidia.com/...nvlink-fusion-xpu-ai-factory
- ^1 ^2 ^3 ^4 ^5 ^6 ^7NVIDIA. "NVIDIA NVLink Fusion Expands With NVHBM Custom High-Bandwidth Memory." NVIDIA Blog, August 26, 2026. blogs.nvidia.com/...m-custom-high-bandwidth-memory
- ^1 ^2 ^3 ^4 ^5 ^6 ^7NVIDIA. "AWS Integrates AI Infrastructure With NVIDIA NVLink Fusion for Trainium4 Deployment." NVIDIA Technical Blog, December 2, 2025. developer.nvidia.com/...n-for-trainium4-deployment
- ^1 ^2 ^3 ^4NVIDIA. "d-Matrix Adopts NVIDIA NVLink Fusion for Rack-Scale XPU Deployment." NVIDIA Blog, September 10, 2026. blogs.nvidia.com/...d-matrix-nvlink-fusion
- ^1 ^2NVIDIA. "NVIDIA and MediaTek Deepen Long-Standing Partnership to Build AI Edge to Cloud Computing Platforms." NVIDIA Newsroom, August 31, 2026. nvidianews.nvidia.com/...cloud-computing-platforms
- ^1 ^2 ^3 ^4 ^5d-Matrix. "d-Matrix Adopts NVIDIA NVLink Fusion Rackscale Infrastructure for Ultra-Low Latency AI Inference." d-Matrix newsroom, September 10, 2026. d-matrix.ai/...d-matrix-rackscale-nvidia
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Cite this page: AI Wiki. "NVLink Fusion." aiwiki.ai, updated 15 Sept 2026, fact-checked 15 Sept 2026. CC BY 4.0. https://aiwiki.ai/wiki/nvlink_fusion