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RISC-V (pronounced "risk-five") [6] is an open standard instruction set architecture (ISA), the contract that defines which instructions a processor executes and which registers software can see. It began as a research project at the University of California, Berkeley, whose first public specification was published as technical report UCB/EECS-2011-62 on 13 May 2011 by Andrew Waterman, Yunsup Lee, David Patterson and Krste Asanović [1]. The specification is now maintained by RISC-V International, a non-profit incorporated in Switzerland in March 2020, which describes RISC-V as "an open, royalty-free ISA" [2].

The commercial difference from Arm and x86 is licensing rather than technology: anyone can implement RISC-V in silicon without negotiating an architecture license or paying per-chip royalties [2]. That property, plus a modular design in which a small base integer ISA is extended by optional feature sets, made RISC-V attractive to companies building custom accelerators, where a control processor is a component rather than a product.

For artificial intelligence hardware, RISC-V shows up in two distinct roles. The visible one is a general-purpose CPU that hosts AI workloads, which is the target of work by SiFive, Alibaba's XuanTie unit and others. The far larger one by volume is invisible to application programmers: small RISC-V cores embedded inside AI accelerators and GPUs as sequencers, data movers and management processors. NVIDIA said that in 2024 it passed the one billion mark for such cores shipped [9].

Origins at Berkeley

RISC-V International dates the work to May 2010, when Krste Asanović and the graduate students Yunsup Lee and Andrew Waterman started the instruction set inside the Parallel Computing Laboratory (Par Lab) at UC Berkeley, a lab directed by David Patterson [2]. The 2011 manual states the original purpose plainly: "RISC-V is a new instruction set architecture (ISA) designed to support computer architecture research and education" [1]. Its stated goals were to provide a "realistic but open ISA that captures important details of commercial general-purpose ISA designs", a small but complete base that avoids over-architecting for any one microarchitecture style, support for both 32-bit and 64-bit address spaces, dense variable-length encoding, and full virtualizability [1].

The name is a joke with two layers. A commentary block in the manual explains that RISC-V "was chosen to represent the fifth major RISC ISA design from UC Berkeley (RISC-I, RISC-II, SOAR, and SPUR were the first four)", and adds: "We also pun on the use of the Roman numeral 'V' to signify 'variations' and 'vectors', as support for a range of architecture research, including various data-parallel accelerators, is an explicit goal of the ISA design" [1]. Data-parallel acceleration was therefore part of the brief from the beginning, which is one reason the architecture fitted AI hardware later without being retrofitted for it.

The base programmer's model has stayed recognizable since that first document: 31 general-purpose registers x1 to x31, with x0 hardwired to zero, and 32-bit or 64-bit register width depending on whether the implementation is RV32 or RV64 [1]. The Berkeley team also stated an intent to release the supporting infrastructure, including documentation, compilers, operating system ports and simulators, "under open licenses (either modified BSD or GPL/LGPL)" [1].

Governance and the open standard model

The RISC-V Foundation was established in 2015 with 36 founding members, and the organization later became RISC-V International, incorporated in Switzerland in March 2020 [2]. Accounts of the timing differ: an analysis by the Jamestown Foundation describes the body as "domiciled in Switzerland since 2019 to avoid technology transfer restrictions from the United States" [25], while RISC-V International's own history gives March 2020 for the incorporation [2]. Either way, the move has been read ever since as a hedge against American export controls reaching the standard itself. The organization itself says only that it "does not take a political position on behalf of any geography" [2].

RISC-V is an open standard, not open-source hardware. The specification is free to read and implement, but most implementations are commercial products: SiFive alone says its licensable cores appear in more than 500 designs [19]. Other implementations are published openly. OpenTitan, an open-source silicon root of trust stewarded by the non-profit lowRISC and built on the Ibex RISC-V core, ships in Chromebooks [31].

The organization's technical output is a library of ratified specifications. Opened in May 2026, that library gathers every ratified RISC-V specification into six groupings: core architecture, profiles, hardware, debug/trace/RAS, platform software, and application enablement [7]. The instruction set manual itself is split into three volumes: unprivileged architecture, privileged architecture, and profiles [5]. At the RVA23 ratification in October 2024, then chief executive Calista Redmond said the community "has grown tremendously to more than 16,000 engineers around the world" [3]. Andrea Gallo, who was vice president of technology at the time of that ratification [3], is chief executive as of 2026 [8].

Base ISA plus extensions

A RISC-V implementation starts from a base integer ISA (RV32I or RV64I) and adds optional standard extensions, each identified by a letter. The common ones are summarized below [6].

LetterAdds
IBase integer instructions
MInteger multiply and divide
AAtomic memory operations
F / DSingle and double precision floating point
CCompressed 16-bit encodings
GShorthand for the IMAFD base and extensions plus Zicsr and Zifencei
VVector operations
BBit manipulation
HHypervisor support for virtualization

Version 1.0 of the vector extension was published on 20 September 2021 and frozen for public review as part of ratification [4]. Vectors matter for AI because the same instructions that accelerate scientific code also cover the elementwise and reduction work around matrix multiplication.

Modularity creates its own problem: a chip that implements an arbitrary subset is hard to target with a single binary. RISC-V International's answer is profiles, which fix a mandatory set of extensions for a class of systems. The RVA23 profile was ratified on 21 October 2024 and makes both the vector extension and the hypervisor extension mandatory for application processors [3]. Andrea Gallo framed it as the fix for portability: "Profiles are the foundations of application and systems software portability across RISC-V implementations" [3]. Lars Bergstrom, a director of engineering at Google, said in the same announcement that the profile "is now the baseline requirement for the Android RISC-V Application Binary Interface (ABI)" [3].

Matrix instructions are the current frontier. Three separate task group efforts exist in the RISC-V GitHub organization: an integrated matrix extension, a vector matrix extension, and an attached matrix extension, all still under active development in mid-2026 [22]. The attached matrix extension grew out of Alibaba XuanTie's in-house matrix-multiply extension, whose team then started a task group "to collaboratively define a standard matrix extension instruction set"; the case made for it is that matrix computing "allows for greater data reuse, which reduces bandwidth demands and enhances energy efficiency by minimizing data transfers" [21].

RISC-V inside AI hardware

The densest concentration of RISC-V cores is not in laptops but inside accelerators, where they run firmware, schedule data movement and drive fixed-function units.

ProductRole of RISC-VDetail
NVIDIA GPUs and SoCsEmbedded microcontrollers10 to 40 cores per chip; passed 1 billion shipped in 2024 [9]
Tenstorrent BlackholePer-tile control processors plus host-class cores5 small RISC-V cores per Tensix tile; 16 SiFive X280 cores on-die [11][12]
Meta MTIA v1Processing element controlTwo customized RISC-V cores per element, one with the vector extension [14]
Esperanto ET-SoC-1Compute cores themselvesOver a thousand RISC-V processors on one TSMC 7 nm die [15]
Google Coral NPUScalar front end driving vector and matrix unitsRISC-V front end with an RVV 1.0 vector unit [16]

NVIDIA's use is the largest by unit count. Frans Sijstermans, the company's vice president of multimedia architecture, told the RISC-V North America summit that in 2024 NVIDIA passed one billion RISC-V processors shipped, with between 10 and 40 per chip depending on configuration, handling function-level control for video codecs, displays and memory controllers, chip-level tasks such as power management and security, and data processing work including packet routing and deep learning network activation. These cores replaced NVIDIA's earlier proprietary Falcon microcontrollers starting in 2016 [9].

NVIDIA has also gone the other way, treating RISC-V as a host rather than an implementation detail. At RISC-V Summit China in 2025 the company disclosed a port of CUDA in which a RISC-V CPU runs Linux and the driver stack while GPUs do the compute. Sijstermans credited the profile work for making it viable, saying "we wouldn't have considered this without RVA23" because it supplied a stable hardware target [10].

Tenstorrent's design is the clearest case of RISC-V as accelerator plumbing. Each Tensix tile contains five small cores that the company's own documentation calls "Baby" RISC-V CPUs: two data-movement cores drive the tile's two network-on-chip interfaces and three drive the unpack, math and pack stages, issuing commands to the matrix and vector units rather than doing the arithmetic themselves [11]. The Blackhole generation lays down 140 such tiles, of which 120 or 140 are enabled depending on the product, alongside four L2CPU tiles, "each one containing a coherent cluster of four SiFive x280 CPUs (for an aggregate total of sixteen CPU cores)" [12]. Counting both classes, The Register reported 752 small cores plus 16 large ones, 768 in total, on a part rated at 745 teraFLOPS of FP8 with 32 GB of GDDR6 [13]. Tenstorrent also has its own high-performance RISC-V CPU core line, Ascalon, for which third-party debug and trace support was announced in August 2025 [32].

Meta's first-generation MTIA accelerator, built on TSMC 7 nm at 800 MHz and 25 W, put "two processor cores (one of them equipped with the vector extension)" in each processing element, and states that "the processor cores are based on the RISC-V open instruction set architecture (ISA) and are heavily customized" [14].

Esperanto Technologies pushed the idea furthest by making the RISC-V cores the compute array rather than the control path, fitting "over a thousand RISC-V processors on a single TSMC 7nm chip" in its ET-SoC-1 for inference workloads [15]. It is also a cautionary example: the company's own site now states that it has ceased operations and that its intellectual property was acquired by Nekko.ai [15].

Google open-sourced a RISC-V based NPU design in October 2025. Coral NPU is "based on a set of RISC-V ISA compliant architectural IP blocks", pairing "a lightweight, C-programmable RISC-V frontend" with a vector unit compliant with "the RISC-V Vector instruction set (RVV) v1.0" and a quantized outer-product multiply-accumulate engine, aimed at all-day on-device AI in wearables and phones [16]. Synaptics was the first to put it in silicon, in its Astra SL2610 series; Billy Rutledge, Google's director of edge AI research, described the release as "an attempt to try to de-fragment the ecosystem of MPUs" [17].

On the CPU side, SiFive, founded in September 2015 by Krste Asanović, Yunsup Lee and Andrew Waterman [33], three of the four authors of the 2011 Berkeley manual [1], says its IP appears in more than 500 designs with over 10 billion cores shipped, and raised $400 million on 9 April 2026 at a $3.65 billion valuation, with investors including Atreides Management, Apollo Global Management and NVIDIA [19]. In January 2026 it announced it would integrate NVLink Fusion so RISC-V CPUs can attach coherently to NVIDIA accelerators, with Jensen Huang describing the combination as "the flexibility to combine customizable RISC-V CPUs with NVIDIA accelerators" [18]. Its second-generation Intelligence cores, such as the X160 shown at Embedded World 2026, combine scalar, vector and matrix compute in one core for edge AI [20]. Andes Technology, whose chief executive Frankwell Lin said RVA23 "will further accelerate the large RISC-V software ecosystem" [3], sells smaller cores for battery-powered devices: its AndesCore D25F is in the Amazfit T-Rex 3 Pro smartwatch, which has shipped over a million units globally [20].

China, sovereignty and export controls

RISC-V's licensing model makes it attractive wherever access to Western IP is politically fragile, which is why China's chip sector adopted it early. In a December 2023 analysis, the Jamestown Foundation reported that the China RISC-V Alliance was created under the Chinese Academy of Sciences in November 2018 and chaired by Ni Guangnan, that more than 300 Chinese companies were developing RISC-V products, that 12 of the 22 premier-level members of RISC-V International were Chinese against 7 American, and that "in 2022, over 50 percent of the 10 billion RISC-V cores manufactured in the world came from China" [25].

Policy support followed. In March 2025 The Register, citing Reuters, reported that eight Chinese government bodies were preparing guidance to encourage widespread use of RISC-V across the country, consistent with earlier direction to avoid American semiconductors [23]. In late February 2025, Alibaba's XuanTie unit had unveiled the C930, a licensable 64-bit out-of-order core compatible with RVA23 and pitched at servers, PCs and vehicles, with a claimed SPECint2006 score above 15 per GHz [23]. A successor, the C950, was reported in March 2026 at up to 3.2 GHz on a 5 nm process, with vector, vector-crypto and attached-matrix support aimed at edge AI and cloud workloads [24]. At the RISC-V Industry Development Conference in December 2025, Ni Guangnan said RISC-V "is becoming an essential foundation for compute innovation in the AI era" [26].

Europe has funded its own effort. In December 2022 EuroHPC opened a framework partnership agreement worth 270 million euros, half from EuroHPC and half expected from member states, to develop RISC-V processors and accelerators for supercomputers over six years, with test hardware required to run in at least one European supercomputing center [27].

Limitations and criticism

The freedom to add custom instructions is also the main source of trouble. Researchers at the CISPA Helmholtz Center for Information Security disclosed GhostWrite, tracked as CVE-2024-44067, in the T-Head XuanTie C910 and C920 cores, and published the work at ACM CCS 2025. Faulty instructions in the vendor's vector extension allowed an unprivileged attacker "to read and write any part of the computer's memory and to control peripheral devices", bypassing the process isolation the operating system normally enforces. Affected parts include the TH1520 and SOPHON SG2042 systems on chip [28]. The bug was in a vendor implementation rather than the standard, which is precisely the failure mode critics of a highly extensible ISA predict.

Software maturity remains the other constraint. Profiles only started to bite recently: RVA23 was ratified at the end of 2024, and RISC-V International's own AI market analysis expected RVA23 hardware in 2026 [29]. Ports of the tooling that AI work depends on, including CUDA, Red Hat and Ubuntu, are recent enough that SiFive listed accelerating them as a use of its 2026 funding round [19].

Being royalty-free also does not make chips cheap. The SHD Group's 2026 RISC-V market forecast projects RISC-V CPU IP revenue of roughly $1.9 billion in 2031 against $318 billion of RISC-V-based SoC revenue [30]. The architecture license was never the expensive part; design, verification, fabrication and software are.

Market outlook

The SHD Group's 2026 forecast, prepared by principal analyst Richard Wawrzyniak, projects 35.9 billion RISC-V SoC units shipping in 2031, generating about $318 billion. Its striking claim is the mix: AI accelerators account for 9.06 billion of those units, roughly a quarter of volume, but around $222 billion of revenue, close to 70 percent of the total [30]. Whether or not the exact figures hold, they describe how the architecture's center of gravity has shifted from microcontrollers toward AI silicon, where a free-to-implement ISA that tolerates aggressive customization is worth more than binary compatibility with existing software.

See also

References

  1. ^Waterman, A., Lee, Y., Patterson, D., Asanović, K. "The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA", UC Berkeley technical report UCB/EECS-2011-62, 13 May 2011. www2.eecs.berkeley.edu/...EECS-2011-62
  2. ^RISC-V International, "About RISC-V". riscv.org/about
  3. ^RISC-V International, "RISC-V Announces Ratification of the RVA23 Profile Standard", 21 October 2024. riscv.org/...ication-of-the-rva23-profile-standard
  4. ^RISC-V vector extension specification, release v1.0, 20 September 2021. github.com/...releases
  5. ^RISC-V ISA manual repository (volumes I to III and ratified version policy). github.com/...riscv-isa-manual
  6. ^Wikipedia, "RISC-V" (extension letters and status summary). en.wikipedia.org/...RISC-V
  7. ^Traynor, B. "We Created a Single Source for All RISC-V Specifications", RISC-V International, 7 May 2026. riscv.org/...ratified-specifications-library
  8. ^Gallo, A. "Call for Candidates: Help Us Build a Board That Represents Our Entire Ecosystem", RISC-V International, 8 May 2026. riscv.org/...2026-elections
  9. ^RISC-V International, "How NVIDIA Shipped One Billion RISC-V Cores In 2024", 25 February 2025. riscv.org/...pped-one-billion-risc-v-cores-in-2024
  10. ^De Vile, J. "NVIDIA on RVA23: 'We Wouldn't Have Considered Porting CUDA to RISC-V Without It'", RISC-V International, 7 August 2025. riscv.org/...nvidia-cuda-rva23
  11. ^Tenstorrent, "TT Architecture and Metalium Guide" (Tensix core and Baby RISC-V cores). github.com/...METALIUM_GUIDE.md
  12. ^Tenstorrent, "tt-isa-documentation", Blackhole A0 architecture overview. github.com/...README.md
  13. ^The Register, "Tenstorrent's Blackhole chips boast 768 RISC-V cores and almost as many FLOPS", 27 August 2024. theregister.com/...tenstorrent_ai_blackhole
  14. ^Meta, "MTIA v1: Meta's first-generation AI inference accelerator", 18 May 2023. ai.meta.com/...ining-inference-accelerator-AI-MTIA
  15. ^Esperanto Technologies, company website (ET-SoC-1 description and notice of ceased operations). esperanto.ai
  16. ^Google Research, "Coral NPU: A full-stack platform for edge AI", 15 October 2025. research.google/...full-stack-platform-for-edge-ai
  17. ^RISC-V International, "EETimes: Google Open-Sources NPU IP, Synaptics Implements It", 29 October 2025. riscv.org/...ources-npu-ip-synaptics-implements-it
  18. ^SiFive, "SiFive to Power Next-Gen RISC-V AI Data Centers with NVIDIA NVLink Fusion", 15 January 2026. sifive.com/...sifive-nvidia-nvlinkfusion-datacenter
  19. ^SiFive, "SiFive Raises $400 Million to Accelerate High-Performance RISC-V Data Center Solutions", 9 April 2026. sifive.com/...ormance-risc-v-data-center-solutions
  20. ^RISC-V International, "Production-Ready, Automotive-Grade, AI-Native: RISC-V at Embedded World 2026", March 2026. riscv.org/...embedded-world-2026
  21. ^RISC-V International, "Enhancing the Future of AI/ML with Attached Matrix Extension". riscv.org/...-ai-ml-with-attached-matrix-extension
  22. ^RISC-V GitHub organization, matrix extension repositories (attached, integrated and vector matrix extensions). github.com/...repositories
  23. ^Sharwood, S. / The Register, "As Alibaba launches server-grade RISC-V CPU, Beijing throws its weight behind ISA", 5 March 2025. theregister.com/...china_alibaba_risc_v_c930
  24. ^Circuit Digest, "Alibaba unveiled XuanTie C950 high performance RISC-V core for edge AI", March 2026. circuitdigest.com/...mance-risc-v-core-for-edge-ai
  25. ^Cheung, S. "Examining China's Grand Strategy for RISC-V", Jamestown Foundation China Brief, 15 December 2023. jamestown.org/...-chinas-grand-strategy-for-risc-v
  26. ^RISC-V International, "Notes From the 2025 RISC-V Industry Development Conference", 5 December 2025. riscv.org/...2025-industry-dev-conference
  27. ^heise online, "270 Millionen Euro fuer CPUs und Beschleuniger: EuroHPC foerdert RISC-V-Technik", 21 December 2022. heise.de/...ro-fuer-CPUs-und-Beschleuniger-7434898
  28. ^Thomas, F., et al. "GhostWrite" (CVE-2024-44067), CISPA Helmholtz Center for Information Security; paper "RISCover: Automatic Discovery of User-exploitable Architectural Security Vulnerabilities in Closed-Source RISC-V CPUs", ACM CCS 2025. ghostwriteattack.com
  29. ^Shkurti, M. "RISC-V: The AI-Native Platform for the Next Trillion Dollars of Compute", RISC-V International, 5 September 2025. riscv.org/...risc-v-ai-native
  30. ^De Vile, J. "Behind The Scenes of SHD Group's 2026 RISC-V Market Forecast", RISC-V International, 19 June 2026. riscv.org/...shd-forecast-2026
  31. ^OpenTitan project website (open-source silicon root of trust, Ibex core, shipping in Chromebooks). opentitan.org
  32. ^RISC-V International, "Ashling Announces RiscFree Debug and Trace Support for Tenstorrent TT-Ascalon RISC-V CPUs", August 2025. riscv.org/...or-tenstorrent-tt-ascalon-risc-v-cpus
  33. ^Wikipedia, "SiFive" (founding date and founders). en.wikipedia.org/...SiFive

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