AMD EPYC Venice

AMD EPYC Venice is the codename for AMD's sixth-generation EPYC server processor, built on the Zen 6 core architecture and launched commercially as the AMD EPYC 9006 Series at Advancing AI 2026 in San Francisco on 2026-07-22 and 2026-07-23.^[1][2] It succeeds the fifth-generation EPYC 9005 "Turin" (Zen 5). Venice is notable on two counts: AMD describes it as the first high-performance computing (HPC) product in the industry to tape out and then enter volume production on TSMC's N2 (2nm-class) process,^[5][6][4] and it is the host CPU of AMD's Helios rack-scale AI system, where 18 Venice CPUs sit alongside 72 Instinct MI455X GPUs in a single rack.^[1] The flagship part, the EPYC 9996, carries 256 Zen 6c cores and 512 threads with 1,024 MB of L3 cache in one socket, which AMD states is more cores and threads than any other publicly disclosed single-socket CPU as of July 2026.^[2] SP7 systems are scheduled to ship in the fourth quarter of 2026, with the remaining Venice product lines following through 2027.^[7] Venice is a server CPU and should not be confused with AMD's Instinct accelerators, which are the GPUs it hosts.

Overview

Venice is the CPU half of AMD's 2026 data center platform refresh. In AMD's product hierarchy it is the general-purpose host and orchestration processor, while the heavy AI math runs on the Instinct GPUs. AMD first attached the Venice name to a manufacturing milestone in April 2025, when it announced that the chip was the first HPC product taped out and brought up on TSMC's N2 node.^[5][6] It previewed Venice as the host CPU for its Helios AI rack in June 2025, displayed working silicon publicly for the first time at CES 2026, announced the start of volume production in May 2026, and launched the family in July 2026.^{[4][16][17][1]}

AMD's marketing frame for the generation is agentic AI. The company's argument, set out in its own launch blog, is that an agent workflow spends most of its wall-clock time outside the model: parsing requests, assembling context, planning and routing, querying databases, invoking tools, verifying output, and streaming responses. Those stages run on CPUs, not accelerators, so AMD positions thread count, memory bandwidth and I/O as the constraint on how many agents a rack can host.^[3] Whether that framing survives contact with real deployments is an open question, and the numbers AMD published to support it are its own; see the performance section below.

Zen 6 architecture and process

Venice is the server implementation of AMD's Zen 6 microarchitecture. As with prior EPYC generations, AMD ships two core flavors: a standard Zen 6 core tuned for clock speed and per-thread performance, and a density-optimized Zen 6c core that trades clock headroom for more cores in the same area. The two share an instruction set and socket family but use different core complex dies (CCDs). AMD's published SKU list makes the split visible: high-frequency parts top out at 96 cores and 5 GHz max boost, while the dense parts reach 256 cores at a 4.1 GHz max boost.^[2]

The compute chiplets are fabricated on TSMC's N2 process, the foundry's first 2nm-class node to use gate-all-around (nanosheet) transistors.^[5] AMD's claim to being first on N2 is specific: it says Venice is the first high-performance computing product to tape out, bring up, and then enter volume production on the node, not the first chip of any kind.^[5][4] Production is ramping in Taiwan, with AMD stating plans to also ramp at TSMC's Arizona fabrication facility.^[4]

Coverage of AMD's launch die shots describes eight CCDs arranged around two central I/O dies, with each dense CCD carrying 32 Zen 6c cores.^[18] The same outlet's launch write-up puts the flagship package at roughly 203 billion transistors and the I/O dies on a 6 nm process, with only the compute chiplets on N2.^[29] AMD publishes neither figure in its own specifications, so both should be treated as reported rather than confirmed. Earlier reporting indicated the standard Zen 6 CCD carries 12 cores (up 50% from the 8-core Zen 5 CCD) with around 48 MB of L3 cache,^[20] while the dense Zen 6c CCD packs 32 cores.^[21] AMD's own cache figures are consistent with that arithmetic: 96-core standard parts list 384 MB of L3 (eight CCDs at 48 MB), and the 256-core 9996 lists 1,024 MB (eight CCDs at 128 MB).^[2]

Press analysis of the CES 2026 hardware described a significant packaging change. Rather than routing CCD-to-I/O traffic through the organic package substrate as earlier EPYCs did, Venice appears to use a more advanced 2.5D-class package with two central I/O dies flanked by up to eight CCDs, a layout closer to AMD's MI-series accelerators than to past server CPUs.^[16][17] AMD has not published the full packaging details.

AMD also changed how it reports power with this generation. Its endnote EPYC-070 states that "Default CPU Power" succeeds TDP as the reference figure for 6th Gen EPYC, and reflects total power across the compute and I/O dies at a stated performance target.^[2] Cross-generation power comparisons therefore mix two different measures.

Product lines and specifications

AMD split Venice into four product lines rather than a single performance ladder, each aimed at a different job.^[1][7][8]

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Note that "Verano" is a member of the sixth generation, not a successor generation. AMD described it in May 2026 as "a 6th Gen EPYC processor optimized for performance-per-dollar-per-watt leadership" using LPDDR memory for power-constrained workloads,^[4] and at launch it appeared as the EPYC 9006 LP line.^[1][8]

Platform-level figures apply across the family. AMD states up to 16 channels of DDR5 with JEDEC-standard MRDIMM support to 12,800 MT/s and PCIe Gen 6 connectivity, with boost frequencies up to 5 GHz on select SKUs.^[2][3] Its own SP7 model pages put per-socket memory bandwidth at 1,638 GB/s with MRDIMMs at 12,800 MT/s and 1,024 GB/s with DDR5-8000 RDIMMs, against the 614 GB/s AMD lists for Turin's 12 channels of DDR5-6400.^[2] Lane counts need more care. Launch coverage reports 128 lanes of PCIe Gen 6 in a single socket and up to 160 in a two-socket system, plus CXL 3.1 memory expansion.^[7][11][13] AMD's own per-model pages disagree with that for the densest parts: they list PCIe 6.0 x96 for the EPYC 9996, 9966 and 9846 and PCIe 6.0 x128 for the 9756, 9656, 9686F and 9586F.^[2] Pre-launch leaks of the SP7 platform documentation had also given 96 Gen 6 lanes for one socket and 128 across two, so the lower figure is not new.^[19] StorageReview called Venice the first server CPU with PCIe Gen 6, which is true only among merchant x86 parts: AWS made the PCIe Gen 6 Graviton5 generally available on 2026-06-10, a quarter before the first Venice systems are due.^[7][30] Intel's Diamond Rapids, which also supports the standard, is not due until 2027.^[23]

The table below lists a selection of announced SP7 SKUs, taken from AMD's published specifications. AMD marks these as subject to change.^[2]

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AMD's efficiency endnote 9xx6-014 also references an "EPYC 9956 (400W Default CPU Power)" that appears nowhere in the published lineup: AMD's product page for that model number returns a 404, and the only 400 W SP7 part AMD lists is the 96-core EPYC 9656 in the table above. The endnote looks like a transposition.^[1][2]

Socket dimensions remain reported rather than officially published. Trade coverage of socket drawings from a Taiwanese component maker gives the SP7 socket a body size of about 123.6 x 100.6 mm, described there as roughly 12% larger than SP5, and the SP8 socket at about 123.9 x 80.9 mm, about 7% larger than SP6. AMD itself publishes no socket dimensions.^[31]

Performance claims

Every performance figure AMD published for Venice at launch is vendor-reported, and much of it is explicitly modeled or projected rather than measured. No independent benchmark results had been published as of 2026-07-27; Phoronix said it intended to run unrestricted third-party benchmarks.^[13]

The most fully documented claim is in AMD's agentic AI blog. Under endnote 9xx6-048, AMD reports a consolidated geometric mean across five CPU-centric pipeline tiers, normalized so that a single-socket Intel Xeon 6980P equals 1.00: EPYC 9755 at 1.36x, EPYC 9965 at 1.82x, AWS Graviton5 at 1.08x, and EPYC 9996 at 2.74x, which AMD describes in the text as a 174% uplift over the Xeon part. The per-tier spread runs from 2.38x on vector similarity search to 3.45x on context assembly, planning and verification. All systems ran Ubuntu 24.04.4 LTS with the performance governor; the EPYC 9996 used DDR5-8000 RDIMMs on an AMD reference platform, while the Xeon and older EPYC systems used DDR5-6400. The Graviton5 numbers came from a public AWS bare-metal instance rather than AMD's lab.^[3]

AMD's rack-level chart is weaker evidence. Under endnotes EPYC-067 and 9xx6-021, AMD projects overall rack performance inside a 100 kW power budget as EPYC 9996 up to 3.3x, EPYC 9965 up to 2.37x, and Intel Xeon 6980P up to 1.46x, against NVIDIA Vera at 1.0. Read the endnote and much of that gap is core count rather than architecture: the node underneath it is a two-socket EPYC 9996 with 512 total cores against a two-socket Vera board with 176, so AMD starts with about 2.9x the cores before any per-core advantage is counted. AMD's own wording describes the result as "preliminary performance estimates based on AMD engineering projections or measurements as of July 22, 2026," built from a geometric mean of six workloads including an estimated SPECrate 2017_int_base score.^[2][7] Tom's Hardware reported that AMD does not have Vera silicon and derived the Vera figures by scaling published results rather than measuring them.^[12] Analyst Matt Kimball of Moor Insights and Strategy made the same point, noting that AMD's rack-level figures are derived numbers built on estimated scaling factors, and advised buyers to run their own proof-of-concept tests with realistic orchestration layers before committing to a refresh.^[9]

Two further AMD claims are arithmetic rather than measurement. Endnote 9xx6-012 states that an EPYC 9996 rack provides 2.08x the cores of an 88-core NVIDIA Vera rack at the same 100 kW envelope, and endnote 9xx6-013 compares 512 threads per socket against 384 on EPYC 9005 and 256 on Intel Xeon 6.^[1] The agents-per-watt endnote, 9xx6-014, models Vera at a 450 W TDP, which is the top of the 250 W to 450 W configurable range NVIDIA publishes; a lower setting would let more Vera sockets fit the same rack.^[1][25] AMD's agent-count figures are, by its own admission, "estimates derived from available CPU thread resources used as a proxy under a consistent theoretical workload."^[2]

AMD's pre-launch roadmap guidance, repeated widely in 2025 and 2026, was more than 70% higher performance and efficiency than Turin and more than 30% greater thread density.^[14][15] The thread-density half is straightforward arithmetic: 512 threads against 384 is a 33% increase. Trade coverage of the launch reported additional AMD claims of roughly 20% higher per-core performance and about 2.2x socket-level throughput against NVIDIA Vera on SPECrate, both run with the same compiler on both sides.^{[7][9][10][11]} The two numbers describe different chips: the per-core figure uses a 96-core high-frequency Venice, while the 2.2x throughput figure uses the 256-core 9996, which carries roughly 2.9 times Vera's cores.^[11] Igor's Lab, reporting the same figures, noted that they are manufacturer benchmarks selected to favor AMD's platform.^[10]

Why the host CPU matters in an AI rack

The interesting question about Venice is not its core count but why a GPU rack needs a large CPU at all. AMD's answer, and the reason it renamed the segment "AI host node," is that accelerator utilization is frequently gated by everything happening around the accelerator.

A production inference service does far more than matrix multiplication. It terminates connections and streams tokens back to clients, tokenizes prompts, runs retrieval against vector indexes, executes tool calls and database queries, enforces sandbox isolation between tenants, and stages weights and KV cache between host memory, local storage and GPU memory. Each of those is a CPU, memory-bandwidth or I/O problem. AMD's own workload decomposition names the stages explicitly and benchmarks them with NGINX, tokenizers, FAISS, Redis, MySQL and MongoDB, plus replayed agent tool traces, and it deliberately excludes the GPU-bound reasoning stage from the CPU comparison.^[3]

KV-cache management is the clearest case. As context windows grow, the cache for a long conversation can exceed what is comfortable to hold in HBM, so serving stacks spill it to host DRAM or NVMe and page it back. That makes host memory capacity, the 16-channel memory subsystem, and PCIe Gen 6 lane bandwidth part of the token-generation path rather than incidental plumbing. The same logic applies to retrieval-augmented generation, where the embedding search runs on the CPU while the GPU waits, and to agentic workloads, where large numbers of short-lived sandboxes each consume threads and memory.

This is also why the same argument is being made by every vendor at once. NVIDIA pairs Vera with Rubin, Arm markets its AGI CPU explicitly for "agentic AI infrastructure," and AWS positions Graviton5 as an orchestration layer around models. The disagreement is about how much CPU is the right amount, not whether the CPU matters.

Role in the Helios rack and AI servers

Venice's most visible role is as the host CPU of AMD's Helios rack-scale platform, the company's answer to integrated GPU racks from NVIDIA. Helios is a double-wide, liquid-cooled rack built to the Open Compute Project's Open Rack Wide specification. AMD's launch release states the configuration precisely: 72 Instinct MI455X GPUs and 18 sixth-generation EPYC "Venice" CPUs, connected by AMD Pensando front-end, scale-up and scale-out networking and accelerated by AMD ROCm software.^[1] The rack is organized as 18 compute trays, each holding four GPUs and one single-socket Venice host, plus switching trays.^[8] The reference build does not use the flagship: teardown coverage puts a 96-core EPYC 9006 SP7 part boosting to about 5 GHz in each tray, with sixteen 64 GB DIMMs for 1 TB of host memory and five E1.S SSD slots, and notes that OEMs and hyperscalers can specify up to 256 cores instead.^[32][33] AMD says Helios is in production, with OpenAI expecting to bring racks online beginning in the fourth quarter of 2026 and Meta validating sixth-generation EPYC platforms in its labs.^[1]

In this design the CPU and GPU play complementary roles. The MI400-series accelerators carry the dense matrix math, 31 TB of HBM4 per rack and up to about 2.9 FP4 exaflops,^[8] while Venice supplies host memory bandwidth, PCIe Gen 6 connectivity and many-core throughput to keep those accelerators fed. The scale-up fabric between GPUs uses UALink-class interconnect over Ethernet, and scale-out networking uses Ultra Ethernet. Helios succeeds AMD's earlier MI300- and MI355X-based systems and is the platform AMD positions against NVIDIA's Vera Rubin racks. AMD claims Helios delivers up to 30% more tokens per dollar than the leading competitive solution, a figure its endnote MI400-025 attributes to AMD Performance Labs estimates using a Kimi K2 Thinking workload at 32K input and 8K output against an NVIDIA Vera Rubin NVL72 rack, with hourly pricing projections rather than observed prices.^[1]

Launch timeline

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On the May 2026 ramp, CEO Lisa Su said: "Ramping 'Venice' on TSMC 2nm process technology marks an important step forward in accelerating the next generation of AI infrastructure."^[4]

Roadmap and successors

At Advancing AI 2026 AMD extended its published server roadmap to 2030.^[1] The stated sequence, in AMD's own words, is that next-generation EPYC CPUs based on the Zen 7 architecture arrive in 2028 under the codenames "Florence," "Ferrara" and "Fidenza," followed by "Ravenna" on Zen 8 in 2030. The rack roadmap runs in parallel: a Helios 500 built around Instinct MI500-series GPUs and EPYC "Verano" CPUs with Pensando "Como" and "Monza" networking, then Helios 600 with MI600-series GPUs, EPYC "Ferrara" CPUs and Pensando "Palma" and "Levanzo" networking. These are roadmap statements about unreleased products, and AMD's own cautionary language flags them as forward-looking.

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Competition versus Intel and Arm

Venice arrives into the most crowded server-CPU field in two decades, with viable x86 and Arm options all targeting AI data center sockets.

On the x86 side, AMD's rival is Intel. Intel's density-oriented answer is Xeon 6+ "Clearwater Forest," launched in June 2026 on the Intel 18A process with up to 288 efficiency cores and 576 MB of L3 cache;^[22] it lacks simultaneous multithreading, so its 288 physical cores line up against Venice's 256 Zen 6c cores with 512 threads. Intel's performance-core flagship, Xeon 7 "Diamond Rapids" on 18A-P, brings up to about 192 P-cores, 16-channel memory and PCIe Gen 6, but is not due until 2027.^[23] That cadence gives Venice a roughly one-year lead over Intel's comparable P-core part, while Clearwater Forest contests the density segment in the same window. AMD's launch comparisons largely skipped Clearwater Forest in favor of the older Xeon 6980P, which is worth noting when reading its charts.^[3]

On the Arm side, the competitive set has broadened sharply. NVIDIA pairs its own Arm-based Vera CPU (88 custom "Olympus" cores)^[25] with Rubin GPUs in its racks, the direct analog of Venice's role inside Helios, and AMD singled Vera out as its main target at launch.^[9] Arm has begun selling finished silicon rather than only licensing IP: its AGI CPU carries up to 136 Neoverse V3 cores in a 300 W envelope, co-developed with Meta as lead partner.^[24] AWS made the 192-core Graviton5 generally available in June 2026, and Google's Axion and Microsoft's Cobalt occupy the same hyperscaler-silicon niche.^[26] Ampere Computing, which SoftBank agreed to buy for $6.5 billion in March 2025 and took full ownership of in November 2025,^[27] announced a 512-core "Aurora" design with on-package HBM in 2024.^[28]

Against these, AMD's pitch for Venice rests on x86 compatibility, very high core and thread counts, a large installed EPYC base and the timing advantage of being first to high-volume 2nm. The competitive question is less about raw core count, where several vendors now exceed 200 cores, and more about per-core performance, memory bandwidth, total cost, and how tightly each CPU integrates with the GPUs in a rack. Until third-party benchmarks appear, the ranking rests on vendor slides.

References

1. ^"AAI 2026: AMD Delivers Full-Stack Compute for the Agentic AI Era." AMD Investor Relations, 2026-07-23. ir.amd.com/...stack-compute-for-the-agentic-ai-era
2. ^"AMD EPYC 9006 Series Server CPUs." AMD, accessed 2026-07-27. amd.com/...9006-series
3. ^Nambiar, Raghu. "Agentic AI: AMD EPYC 9005 CPUs Wins Today, EPYC 9006, formerly code-named 'Venice', Takes It to a New Level." AMD Blogs, 2026-07-23. amd.com/...amd-epyc-9005-cpus-wins-today-epyc-9006
4. ^"AMD Announces Production Ramp of Next-Generation AMD EPYC Processor 'Venice' on TSMC 2nm Process Technology." AMD Investor Relations, 2026-05-21. ir.amd.com/...enice-on-tsmc-2nm-process-technology
5. ^"AMD Achieves First TSMC N2 Product Silicon Milestone." AMD Investor Relations, 2025-04-14. ir.amd.com/...st-tsmc-n2-product-silicon-milestone
6. ^"AMD Tapes Out 1st HPC Product on TSMC 2nm Process with 'Venice' EPYC CPU." HPCwire, 2025-04-14. hpcwire.com/...mc-2nm-process-with-venice-epyc-cpu
7. ^"AMD 6th Gen EPYC Venice: 256 Cores, 1.6TB/s, and the First PCIe Gen 6 Server CPU." StorageReview, 2026-07. storagereview.com/...e-first-pcie-gen-6-server-cpu
8. ^"AMD Ships Helios AI Rack With EPYC 9006 CPUs, Instinct MI400X GPUs And More At Advancing AI 2026." HotHardware, 2026-07. hothardware.com/...pyc-9006-instinct-mi400x-helios
9. ^Kimball, Matt. "EPYC 'Venice' Deep Dive: AMD Goes On Offense In The CPU Market." Moor Insights and Strategy, 2026-07. moorinsightsstrategy.com/...ense-in-the-cpu-market
10. ^"AMD EPYC 9996 'Venice': 256 Zen 6 cores are expected to put pressure on Intel's Xeon and NVIDIA's Vera." Igor's Lab, 2026-07. igorslab.de/...-256-zen-6-cores-pressure-xeon-vera
11. ^"AMD's 256-core Epyc 9996 'Venice' claims up to a 3.4x jump over Intel Xeon competition, 20% over Nvidia Vera." Tom's Hardware, 2026-07. tomshardware.com/...l-memory-and-5ghz-clock-speeds
12. ^"AMD fires back at Nvidia, claiming 256-core Zen 6 'Venice' CPU beats Vera by 3.3x in rack-level performance." Tom's Hardware, 2026-06. tomshardware.com/...timated-epyc-venice-benchmarks
13. ^"AMD EPYC 9006 Venice Announced & Looks Poised To Be A Grand Slam." Phoronix, 2026-07-22. phoronix.com/...amd-epyc-9006-venice
14. ^"AMD begins production ramp of 256-core EPYC Venice, first 2nm HPC chip claims 70% performance leap." Tom's Hardware, 2026-05. tomshardware.com/...-epyc-venice-on-tsmcs-2nm-node
15. ^"AMD EPYC Venice boasts 256 cores and bandwidth galore, next-gen server CPUs arrive in 2026." Tom's Hardware, 2025. tomshardware.com/...in-the-labs-now-coming-in-2026
16. ^"AMD's EPYC Venice, Instinct MI455X, & Helios Hardware On Display for First Time at CES 2026." ServeTheHome, 2026-01. servethehome.com/...lay-for-first-time-at-ces-2026
17. ^"CES 2026: Taking the Lids off AMD's Venice and MI400 SoCs." Chips and Cheese, 2026-01. chipsandcheese.com/...026-taking-the-lids-off-amds
18. ^"AMD's Zen 6 EPYC Venice Pictured as a 256-Core Monster, Massive Twin I/O Dies & First 2nm HPC Chip To Enter Volume Ramp." Wccftech, 2026-07. wccftech.com/...ed-confirms-32-cores-per-zen-6-ccd
19. ^"AMD SP7 & SP8 Platforms For Next-Gen EPYC 'Venice' & 'Verano' CPUs Detailed." Wccftech, 2025. wccftech.com/...-channel-memory-128-pcie-6-0-lanes
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23. ^"Intel Xeon 7 'Diamond Rapids' CPUs officially launching in 2027 on Intel 18A-P." Tom's Hardware, 2026. tomshardware.com/...and-twice-the-memory-bandwidth
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25. ^"Nvidia unveils details of new 88-core Vera CPUs positioned to compete with AMD and Intel." Tom's Hardware, 2026. tomshardware.com/...to-a-6x-gain-in-cpu-throughput
26. ^"Amazon unveils 192-core Graviton5 CPU with massive 180 MB L3 cache in tow." Tom's Hardware, 2026-06. tomshardware.com/...yc-and-intel-xeon-in-the-cloud
27. ^"SoftBank to acquire Arm CPUs for datacenter firm Ampere in $6.5 billion cash deal." Tom's Hardware, 2025-03. tomshardware.com/...re-in-usd6-5-billion-cash-deal
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30. ^"AWS Graviton5 is now generally available, delivering purpose-built performance for the agentic AI era." About Amazon, 2026-06-10. aboutamazon.com/...aws-graviton-5-cpu-amazon-ec2
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32. ^Cozma, George, Aurora Nockert and Nintonito. "AMD's Instinct MI455X: Aiming for the Sun." Chips and Cheese, 2026-07-23. chipsandcheese.com/...stinct-mi455x-aiming-for-the
33. ^Mann, Tobias. "AMD attacks the rack with Helios systems that rival Nvidia's." The Register, 2026-07-23. theregister.com/...5277246