Huawei Ascend 910C
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The Huawei Ascend 910C is a data-center artificial intelligence accelerator developed by Huawei, positioned as China's leading domestic alternative to high-end NVIDIA GPUs that are restricted from sale to Chinese customers under United States export controls. Reported widely through 2024 and 2025, the Ascend 910C is most often described by analysts as a dual-die design that packages two of Huawei's earlier Ascend 910B processors together to roughly double per-package performance. Huawei has said relatively little about the part in formal datasheets, so most of the detailed numbers in circulation come from research firms, supply-chain reporting, and chip teardowns. The figures below should be read as attributed estimates rather than vendor-confirmed specifications.[1][2][6]
The chip matters less for beating NVIDIA on a per-device basis, which analysts generally agree it does not, and more for giving China a credible path to building large AI training and inference clusters without access to the most advanced Western hardware. Its highest-profile use is inside Huawei's CloudMatrix 384, a rack-scale system that strings together 384 of the accelerators and that SemiAnalysis described in April 2025 as China's answer to NVIDIA's GB200 NVL72.[1]
The Ascend 910C exists because of a multi-year tightening of United States export controls aimed at slowing China's access to advanced AI compute. In October 2022, the US Bureau of Industry and Security introduced sweeping rules that, among other things, blocked NVIDIA from selling its A100 and H100 data-center GPUs to customers in mainland China and Hong Kong. NVIDIA responded in 2023 with the cut-down H800, designed to fall under the thresholds, but in October 2023 Washington tightened the rules again and halted H800 exports as well. NVIDIA then built the further-reduced H20 for the Chinese market. In April 2025, the US government told NVIDIA that the H20 would also require an export license, a move NVIDIA said would cost it roughly 5.5 billion dollars in charges, before the administration reversed course in July 2025 and allowed licensed H20 sales to resume.[9][10]
Each round of restriction widened the gap between what Chinese AI developers wanted and what they could legally buy, and that gap created strong demand for a domestic substitute. Huawei, through its HiSilicon design arm, became the most prominent supplier. The Ascend line is the centerpiece of China's broader push for semiconductor self-sufficiency, and the 910C is the generation that brought that effort into direct comparison with NVIDIA's flagship data-center products. The chip is frequently cited in debates over whether export controls slow China's AI progress or mainly accelerate its drive toward homegrown alternatives.[7][10]
The most consistent technical claim about the Ascend 910C, reported by SemiAnalysis and by news outlets including Reuters, is that it is not a single new monolithic chip but two Ascend 910B compute dies packaged together. The goal of that approach is to roughly double the compute and memory of a single 910B without designing an entirely new die, which would be harder given China's constrained access to leading-edge manufacturing.[1][2]
Analysts have compared the packaging concept to NVIDIA's own multi-die B200, in which two dies sit on separate interposers that are then linked through an organic substrate, rather than a single piece of silicon. According to teardown and analyst descriptions, the two 910C dies are connected by a high-bandwidth interconnect so that the package presents itself to software as one accelerator. Some reporting notes that the design also integrates Arm-compatible CPU cores on the package, a feature of the Ascend 910 family that lets it run system-level tasks without leaning entirely on a separate host processor, though the exact configuration in the 910C is not something Huawei has documented publicly.[1][6]
Software is a central part of the picture, and it is one of the few areas where Huawei speaks directly. The company provides its own compute stack, called CANN (Compute Architecture for Neural Networks), as an alternative to NVIDIA's CUDA, along with the MindSpore framework. Porting and optimizing AI workloads for CANN requires extra engineering effort, and the smaller surrounding ecosystem has historically been a barrier to adoption, even among Chinese developers who would otherwise prefer a domestic part. Analysts repeatedly flag software maturity, not raw silicon, as the gap that is hardest for Huawei to close quickly.[4][7]
No official Huawei datasheet pins down the Ascend 910C's throughput, so the widely repeated numbers are reconstructions by analysts. SemiAnalysis and others estimate per-package performance of roughly 780 to 800 teraflops of dense BF16 or FP16 compute. One common derivation works backward from the CloudMatrix 384 system: SemiAnalysis put that 384-chip system at about 300 petaflops of dense BF16, which implies on the order of 781 teraflops per chip.[1][6]
On that basis, several analysts have estimated that a single 910C reaches roughly 80 percent of an NVIDIA H100's BF16 throughput, placing it broadly in the H100 or H800 neighborhood on that one metric while trailing on memory technology, interconnect, energy efficiency, and software. Reporting in April 2025 by outlets summarizing SemiAnalysis noted that a 910C-based system could outperform H100-based setups on certain inference workloads at the cluster level, but the framing was about system scale rather than any claim that the chip itself is faster than NVIDIA's. SemiAnalysis was explicit that, per chip, the 910C is roughly one-third as capable as an NVIDIA Blackwell-generation part, so its competitiveness comes from deploying far more chips rather than from per-device strength.[1][3]
Memory estimates are similarly sourced to analysts. Third-party figures put the 910C at about 128 gigabytes of high-bandwidth memory (variously reported as HBM generations such as HBM2E) with memory bandwidth in the range of 3.2 to 3.5 terabytes per second. Reported package power sits around 310 to 350 watts in various accounts, with some sources cautioning that figures may reflect a single die rather than the full dual-die package. None of these numbers should be treated as confirmed by Huawei.[1][6]
Manufacturing is the most contested and most consequential part of the Ascend 910C story, and it is where the gap between popular shorthand and the detailed analyst account is widest. The common description is that the chip is fabricated by China's leading foundry, SMIC, on a 7-nanometer-class process that SMIC calls N+2. TrendForce, citing Reuters and Commercial Times, reported in late 2024 that the 910C was being produced on that N+2 node with mass production targeted for the first quarter of 2025, and analysts have estimated the design at roughly 53 billion transistors.[2][6]
The more detailed account complicates that picture. SemiAnalysis reported in 2025 that the great majority of Ascend 910B and 910C dies examined were actually made on TSMC's 7nm process, not SMIC's. Independent teardowns by the analysis firm TechInsights reached a similar conclusion, finding TSMC-fabricated dies inside 910C samples. According to multiple reports, Huawei obtained those dies despite TSMC having stopped supplying Huawei in 2020: a Cayman Islands-registered company called Sophgo purchased roughly 500 million dollars of 7nm wafers from TSMC, which were then routed to Huawei, amounting to about 2.9 million dies usable for both the 910B and 910C. US authorities treated the arrangement as a sanctions-evasion scheme; TSMC cut off Sophgo, reported the matter, and faced potential penalties from the US Commerce Department reported to exceed 1 billion dollars.[6][7]
SemiAnalysis framed this stockpile as a TSMC "die bank" that carried Huawei's Ascend production through 2024 and 2025, and projected in its September 2025 analysis that the bank would run down within roughly nine months. Its assessment was that SMIC would no longer be the binding constraint going forward, estimating SMIC advanced-node capacity at around 45,000 wafers per month by the end of 2025, rising to 60,000 in 2026 and 80,000 in 2027, against a need of at most about 20,000 wafers per month to make millions of Ascend dies.[6]
The constraint that analysts emphasized instead was HBM. SemiAnalysis estimated that China had procured around 13 million stacks of foreign high-bandwidth memory, with Samsung as the leading supplier and a large share shipped in a window between the announcement and enforcement of new controls in late 2024. Those stacks were enough for roughly 1.6 million Ascend 910C packages. The firm projected that China could produce on the order of 805,000 Ascend accelerators in 2025 from existing capacity but would be held back by HBM availability, and that domestic HBM from suppliers such as CXMT, estimated at around 2 million stacks in 2026, would support only a few hundred thousand 910C packages, well short of the fabrication potential. In short, the analyst consensus through 2025 was that HBM supply, not chip fabrication, was the gating factor on how many 910C accelerators Huawei could build.[5][6]
Yield was another widely cited concern. TrendForce, again citing Reuters, reported that the 910C's yield was only around 20 percent, far below the roughly 70 percent generally considered viable for commercial production, which constrained how quickly usable parts could come off the line. As with the other figures, this was sourced to supply-chain reporting rather than to Huawei.[2]
The most discussed deployment of the Ascend 910C is the Huawei CloudMatrix 384, often abbreviated CM384, a rack-scale system that links 384 Ascend 910C accelerators with an all-optical interconnect. Unlike most of the chip-level numbers, CloudMatrix is a product Huawei has publicly described and offered, although the comparative performance analysis around it comes mainly from SemiAnalysis. The system spans 16 racks, pairs the 384 accelerators with a large complement of CPUs, and uses optical links rather than copper for communication between chips and racks. Reports describe on the order of 6,900 800G-class optical transceivers carrying traffic across the system.[1]
According to SemiAnalysis, at the system level CloudMatrix 384 delivers more total compute and memory than NVIDIA's GB200 NVL72 rack: roughly 300 petaflops of dense BF16, almost double the NVL72's figure, along with about 3.6 times the aggregate HBM capacity and roughly 2.1 times the aggregate memory bandwidth. The catch is efficiency. SemiAnalysis estimated that CloudMatrix 384 draws about 4.1 times the power of a GB200 NVL72, which works out to roughly 2.5 times worse power per FLOP, about 1.9 times worse power per unit of memory bandwidth, and around 1.2 times worse power per terabyte of HBM. Each individual Ascend chip is far less capable and far less efficient than NVIDIA's silicon; the system wins on aggregate numbers only by using many more chips and a great deal more electricity.[1]
That trade-off is the core of Huawei's strategy. Rather than try to win on per-chip performance or efficiency, the approach is to scale up the number of accelerators and the bandwidth between them so a complete cluster is competitive for training and serving large models. Higher energy consumption is more tolerable in China given relatively abundant and cheaper domestic power. CloudMatrix 384 has been associated in reporting with serving reasoning models such as those from DeepSeek, an example often used to illustrate that a Chinese AI stack can run demanding workloads end to end on domestic hardware.[1][3]
Reporting through 2025 indicated a steady ramp for the Ascend 910C. Reuters and outlets summarizing its reporting said Huawei prepared to begin mass shipments of the 910C to Chinese customers as early as May 2025, with some samples and early units already delivered to technology companies that were placing orders. The reported customer base centered on large Chinese internet and AI firms looking to replace restricted NVIDIA parts in their data centers.[2][8]
The broader context for adoption is uneven supply. Earlier reporting on the predecessor 910B illustrated the pattern: orders far exceeded deliveries, with figures suggesting that of more than 100,000 Ascend 910B chips ordered by one large customer, fewer than a third had been delivered by mid-2024. Analysts continued to note through 2025 that Huawei's ability to manufacture the 910C at the scale required to fully replace restricted NVIDIA hardware was limited, mainly by HBM supply and secondarily by the eventual exhaustion of the TSMC die bank, alongside the persistent software-ecosystem gap.[2][6]
Huawei has also publicly laid out a forward roadmap that puts the 910C in context. At its 2025 Connect conference, the company detailed successor Ascend generations, including the Ascend 950 series slated for 2026, the Ascend 960 for 2027, and the Ascend 970 for 2028, with steadily rising low-precision throughput and accompanying Atlas SuperPoD and SuperCluster systems that scale to hundreds of thousands and then more than a million accelerators. Huawei framed this as a multi-year plan to compete through system scale and frequent iteration rather than through any single chip matching NVIDIA's best. The Ascend 920 has also been reported as a near-term successor aimed at improving on the 910C. These roadmap claims come from Huawei itself and describe future products rather than shipping hardware.[11]
The significance of the 910C is therefore strategic. It is the chip that demonstrated China could field a domestically packaged, large-scale AI accelerator and wrap it in a rack-scale system competitive at the cluster level with NVIDIA's flagship, even while conceding clear losses on per-chip performance, efficiency, and software. It is the practical embodiment of the argument that export controls have reshaped, rather than simply stopped, China's AI compute buildout.[1][7]
Almost everything specific about the Ascend 910C should be read with care. Huawei has not published a full datasheet, so per-chip throughput, memory capacity, bandwidth, transistor count, power draw, yields, and unit volumes are analyst and supply-chain estimates rather than vendor-confirmed numbers. Different sources give different values, for example BF16 compute reported anywhere from about 780 to 800 teraflops and power from roughly 310 to 350 watts, and some figures may conflate a single die with the full package.
The manufacturing story carries the most uncertainty of practical consequence. The popular shorthand that the 910C is "an SMIC 7nm chip" coexists with detailed analyst and teardown findings that most examined dies were actually made by TSMC and stockpiled before controls bit, with SMIC positioned to take over volume production over time. Both can be partly true depending on the production batch and date, which is exactly why the distinction matters. Readers should treat any single confident specification for the 910C as provisional, attribute it to its source, and expect revisions as more teardowns, official disclosures, and shipment data appear.[1][2][6]