SMIC

RawGraph

Semiconductor Manufacturing International Corporation (SMIC) is China's largest contract chipmaker and the most advanced pure-play semiconductor foundry on the mainland, meaning it manufactures integrated circuits designed by other companies rather than selling chips under its own brand. Founded in Shanghai in 2000, it runs fabrication plants in Shanghai, Beijing, Tianjin and Shenzhen, offers both 8-inch (200mm) and 12-inch (300mm) wafer services, and produces logic and specialty chips from mature nodes down to a 7nm-class process that it reaches without extreme ultraviolet (EUV) lithography.[3] TrendForce ranked it third worldwide among foundries in the first quarter of 2026, with US$2.51 billion of revenue and 5.1 percent of the market, behind TSMC and Samsung Foundry.[19]

For an encyclopedia of artificial intelligence, SMIC matters for one reason above all others. It is the only mainland foundry that can currently print the logic dies for China's domestic AI accelerators, so its capacity, its yields and the way it allocates its most advanced wafers set a ceiling on how much AI compute China can build without American permission. Huawei's Ascend line and the products of the listed Chinese accelerator designers, including Cambricon, Biren Technology, MetaX, Moore Threads and Enflame, all depend on the same small pool of SMIC 7nm-class wafers.[15] The broader industrial context, including memory, equipment and the financing model behind it, is covered in China's semiconductor industry.

SMIC has been on the United States Commerce Department's Entity List since December 2020, with a presumption of denial for anything uniquely required to produce semiconductors at 10nm and below, a policy that permanently forecloses EUV.[4] It is separately designated a Chinese military company by the Department of Defense under Section 1260H.[6] Because it cannot buy EUV scanners, it reaches its most advanced nodes with 193nm immersion deep ultraviolet (DUV) equipment and aggressive multi-patterning, an approach that works and has been confirmed in teardowns of shipping products, but that costs mask layers, cycle time, die area and yield on every wafer.[7][9][10]

The company is substantially backed by Chinese state investment vehicles, is listed in Hong Kong (SEHK 00981) and on Shanghai's STAR Market (688981), and reported revenue of US$9.33 billion for 2025 with a 21.0 percent gross margin and US$685 million of profit attributable to owners.[1][3]

History and corporate background

SMIC was incorporated on 3 April 2000 by Zhang Rujing, also known by the English name Richard Chang. Zhang was born in Nanjing in 1948, grew up in Kaohsiung, Taiwan, and spent about two decades at Texas Instruments in the United States before building chip factories in Asia. He founded SMIC as a pure-play foundry modelled on the Taiwanese contract-manufacturing approach, recruiting engineers internationally and equipping the Shanghai site with imported tools.

The company's early years were shaped by litigation with TSMC, the Taiwanese foundry that invented the pure-play model. TSMC sued in 2003 over misappropriation of trade secrets, the parties settled in 2005, and TSMC sued again in California in 2006 alleging further misappropriation and breach of that settlement. The second case was resolved on 10 November 2009. TSMC's own announcement of the settlement states that "SMIC has agreed to make cash payments to TSMC totaling $200 million, which are in addition to $135 million previously paid to TSMC under the 2005 settlement agreement," that SMIC's appeal against a Beijing Higher Court finding for TSMC was dropped, and that the two companies terminated their 2005 patent cross-licensing agreement.[25] Contemporary reporting valued the full package at around US$290 million once the equity component was included, with TSMC receiving stock and warrants that could take it to roughly 10 percent of SMIC. Zhang left the company as part of the settlement.

SMIC held a dual initial public offering on the New York Stock Exchange and the Hong Kong Stock Exchange in 2004. It voluntarily delisted its American depositary shares from the NYSE in 2019, citing low trading volume and high compliance costs, and kept the Hong Kong listing. In July 2020 it completed a secondary listing on the Shanghai Stock Exchange's STAR Market, raising RMB 53.2 billion including the over-allotment. That stood as the STAR Market's fundraising record for six years until CXMT raised RMB 57.92 billion in July 2026.[26] Its largest shareholders are state-linked funds, including the China Integrated Circuit Industry Investment Fund, universally called the Big Fund, which is the same vehicle that anchors most of the country's Made in China 2025 semiconductor programme.

Operationally the company runs under an unusual co-chief-executive structure, with Zhao Haijun and Liang Mong Song serving as co-CEOs. Liang is a former TSMC and Samsung process engineer whose recruitment in 2017 is generally credited with SMIC's FinFET push. Liu Xunfeng is chairman; in the 2025 annual results announcement he described the year as transformative and said the company had maintained a high level of research and development investment while expanding capacity in a steady manner.[1]

Process technology

Most of SMIC's revenue comes from mature and legacy nodes at 28nm and above. These make display drivers, power-management chips, image sensors, microcontrollers, radio-frequency parts and the other high-volume components that do not need leading-edge lithography. SMIC reports capacity in standard logic 8-inch equivalent wafers, and the scale of that mature business is what makes it the anchor of China's domestic chip supply: monthly capacity was 1,078,250 8-inch equivalents at the end of the first quarter of 2026.[20][21]

The company's own disclosures do not break revenue or capacity out by process node, its results releases do not discuss its 7nm-class processes, and it does not name customers. Everything below is therefore either a company statement from an earlier era, an independent teardown, or attributed trade reporting, and the article flags which is which.

The verified roadmap

SMIC's first FinFET node entered mass production in the fourth quarter of 2019. The company's own results release for that quarter says "our first generation of FinFET, 14nm, entered mass production, contributing 1% of wafer revenue for the quarter."[24] Everything more advanced than that is designated internally by an N+ number rather than a nanometre figure, which is itself informative: SMIC does not market these nodes, because marketing them would invite exactly the scrutiny that the Entity List entry already imposes.

GenerationSMIC designationStatus and the evidence for it
28nm and aboven/aHigh-volume production; the core of revenue and capacity[1][3]
14nm FinFETn/aMass production from Q4 2019, 1 percent of wafer revenue that quarter, per SMIC's own release[24]
7nm-class, first generationN+1SMIC's internal designation for its first 7nm-class node. Confirmed by TechInsights in the MinerVa Bitcoin Miner ASIC in July 2022, a low-volume mining part rather than a mass-market consumer product; SemiAnalysis reported SMIC 7nm shipping the same month
7nm-class, second generationN+2Confirmed by TechInsights in the HiSilicon Kirin 9000s (September 2023) and again in the Kirin 9020 (December 2024)[7][8]
7nm-class, third generationN+3Confirmed by TechInsights in the Kirin 9030 (11 December 2025) and measured in detail by SemiAnalysis (14 June 2026)[9][10]
5nm-classN+4 (reported)Not demonstrated in any published teardown. TrendForce reported in December 2025 that N+3 and N+4 yields were "hovering at around 20%"[15]

The distinction between these categories is the whole substance of the SMIC question, and it is routinely flattened in coverage. A node that a foundry has running in a development line is not the same as a node that appears in a torn-down retail product, and neither is the same as a node in profitable volume production.

What "7nm-class" actually means here

The N+2 process became public knowledge on the industry's terms rather than SMIC's. In September 2023 TechInsights tore down the Huawei Mate 60 Pro and found that its Kirin 9000s applications processor, a 107 mm2 die, was built on SMIC's 7nm (N+2) process. TechInsights vice chair Dan Hutcheson said the discovery "demonstrates the technical progress China's semiconductor industry has made without EUV lithography tools."[7] That teardown, not any company announcement, is the origin of essentially every subsequent claim about SMIC at 7nm.

The node then stood still for a generation. When TechInsights examined the Huawei Mate 70 Pro+ in December 2024, it found the Kirin 9020 "fabricated by SMIC on a 7nm (7N+2) process node," sharing its process technology with the Kirin 9010 of the Pura 70 series and representing an incremental change in floorplan rather than a node advance.[8] Roughly fifteen months of Huawei flagship launches produced no lithographic progress at all, which is a useful corrective to the impression that SMIC advances a node every year.

The third generation arrived with the Mate 80 series. On 11 December 2025 TechInsights published an analysis of the Kirin 9030 confirming SMIC N+3, describing it as a scaled evolution of the 7nm-class technology and framing it as "a key indicator of how close SMIC is to achieving a true 5nm-equivalent node without EUV lithography," while noting that N+3 "remains significantly less scaled than leading commercial 5nm nodes offered by TSMC and Samsung."[9]

SemiAnalysis published measured dimensions from its own teardown of a Kirin 9030 Pro on 14 June 2026. The figures are the most precise public description of what SMIC's third-generation node actually is.[10]

MeasurementSMIC N+3Comparison
Minimum metal pitch (M0)32.5 nmTighter than TSMC N6 at about 40 nm; about 10 percent tighter than Intel 18A at 36 nm[10]
Transistor density113.4 MTr/mm2Above TSMC N6 at 107.7 MTr/mm2; roughly 38 percent below Intel 18A's high-density library[10]
Contacted gate pitch57 nm
Standard cell height228 nmTSMC N6 at 240 nm[10]
Fin pitchabout 32 nmFormed by self-aligned quadruple patterning[10]
8T SRAM bitcell0.0463 um2Achieved L3 cache density 23.8 Mib/mm2, system-level cache 25.5 Mib/mm2[10]

Two things follow from that table, and they point in opposite directions. SMIC has reached the transistor density of a mature EUV node without EUV, which is a real engineering achievement. It has done so on a process that is still, by density, a 7nm-class node rather than a 5nm one, and it has paid for the density in ways that show up in the finished product. SemiAnalysis found that the Kirin 9030's prime CPU cores deliver roughly Cortex-X2 class performance per clock, a 2021 design point, and that the Maleoon 935 GPU, while about 70 percent faster than its predecessor, remains 2.4 to 2.6 times slower than current flagship GPUs. Its summary of the trade is that N+3 reaches the density of TSMC N6 "through aggressive DUV multi-patterning and design-technology co-optimization (DTCO), but it pays for that in complexity, efficiency and process control."[10]

The 5nm question

There is no published teardown of any retail product built on a SMIC 5nm-class process. Reports that SMIC is developing one go back to Financial Times coverage in 2024, and trade press through 2025 repeated variants of the claim, generally tied to Huawei's roadmap. The concrete public evidence points the other way for now: TechInsights, examining the most advanced SMIC silicon available in December 2025, positioned N+3 as an indicator of distance still to travel rather than arrival.[9] TrendForce's December 2025 assessment was that N+3 and N+4 yields were around 20 percent, which is why N+2 remained the practical choice for volume production even after the newer nodes existed.[15]

The honest summary is that SMIC almost certainly has 5nm-class development work running, that at least one node beyond N+3 exists in trade reporting under the designation N+4, and that nothing has been shown to be in economic volume production. A "SMIC 5nm" headline unaccompanied by a teardown is a claim about a development line, not about silicon anyone has held.

Manufacturing without EUV

The single binding constraint on SMIC's advanced-node ambitions is lithography. EUV, which patterns with 13.5nm light, is what lets leading foundries define the smallest features at 7nm and below in a single exposure. ASML is the only company that builds and sells EUV systems, and none has ever been delivered to a mainland Chinese customer. Successive Dutch and American rules have narrowed access to immersion DUV as well.

Multi-patterning, and what it costs

Without EUV, SMIC prints its finest layers using 193nm immersion scanners and multi-patterning, in which several lithography, deposition and etch steps combine to define a pitch that no single exposure could resolve. The SemiAnalysis teardown documented exactly which techniques are used where on N+3: self-aligned quadruple patterning (SAQP) on the tightest metal layer and on the fin, self-aligned double patterning (SADP) on metal layers one through three.[10]

Each of those schemes replaces one exposure with a sequence of four or more process steps. That means more masks, more deposition and etch operations, longer cycle time, more places for a defect to originate, and much tighter overlay tolerance, because the position of a feature now depends on the alignment of several separate steps rather than one. SemiAnalysis put it plainly: at a 32.5nm M0 pitch, "DUV patterning requires more aggressive multi-patterning, increasing mask count, overlay sensitivity, process complexity and cost."[10] This is not a problem that goes away with practice. It is structural, and it is the reason that the interesting question about SMIC is never whether it can make a 7nm-class chip but at what cost and in what volume.

The domestic lithography effort

China's answer is a domestic immersion DUV programme, and the chain of custody matters because coverage frequently garbles it. According to Asia Times reporting in July 2026, the SSA800 immersion scanner is Shanghai Micro Electronics Equipment's (SMEE) design; SMEE passed the technology to Shanghai Yuliangsheng in 2025 while retaining its own EUV effort. Yuliangsheng is a joint venture founded in 2022 between SiCarrier and the state-backed Chuangkewei (Shanghai) Technology, and its engineering team has since moved into a separate state-owned vehicle, Shanghai Aishengna, registered in August 2023 with RMB 7 billion of capital. The scanner is therefore not SiCarrier's design, although it is frequently described that way.[22]

The specifications set the expectations. Asia Times reported analysts describing the SSA800 as roughly equivalent to ASML's TWINSCAN NXT:1950i, a tool launched in 2008 for 28nm production, and about four generations behind ASML's current products. Domestic content is around 70 percent, with the 193nm excimer laser mirror, Zeiss lenses, the vacuum chamber, synchronisation control software and the ArF immersion light source all still imported.[22] The Information reported in late July 2026 that limited production had begun, with around five units expected in 2026 and roughly twenty in 2027, and with the first machines going to SMIC, Hua Hong Semiconductor and CXMT.[22] SMIC has been evaluating a Yuliangsheng immersion tool since September 2025.

The most important thing to understand about this programme is that it does not solve the problem this article is about. A domestic immersion scanner equivalent to a 2008 ASML machine would still leave SMIC doing multi-patterning to reach 7nm-class, with all of the mask count, cycle time and yield penalties intact. What it changes is supply security, not process economics. Those are separate questions, and conflating them is the most common error in coverage of SMIC. Independent forecasts published in mid-2026 put a commercially viable domestic immersion scanner capable of supporting 7nm work well into the 2030s; the fuller account of that programme, including unit forecasts and ASML's share of the immersion market, is in the China semiconductor industry article linked above.

Domestic tool substitution has a second-order cost as well. TrendForce noted in December 2025 that SMIC's shift toward domestically sourced equipment was itself "weighing on production-line stability," which is a reminder that swapping a qualified ASML, Applied Materials or Tokyo Electron tool for a NAURA or AMEC equivalent is a process-engineering project rather than a purchase order.[15]

Yields, cost and the economics of DUV multi-patterning

This is the crux of the SMIC question and the part most often skipped. Multi-patterning on DUV raises the number of process steps per wafer, which raises cost per wafer, and it raises defect opportunities, which lowers yield. Both effects compound: a more expensive wafer that produces fewer good dies raises cost per good die twice over. So the interesting metrics are not node names but yield, cost per wafer and wafers per month.

SMIC discloses none of them for its advanced nodes. What exists publicly is a small set of attributed estimates, and it is worth being precise about who made each one and what it measures.

ClaimFigureSource, date and what it actually measures
Huawei Ascend yieldImproved to nearly 40 percent, "doubling from 20% a year ago," with a target of 60 percentFinancial Times reporting relayed by TrendForce, 25 February 2025. This is a claim about Huawei's Ascend production yield overall, not a measured SMIC process yield, and the FT's sources were unnamed industry contacts[13]
N+3 and N+4 yields"Hovering at around 20%"TrendForce, 15 December 2025, offered as the reason N+2 remained the volume node[15]
SMIC 5nm wafer costUp to 50 percent higher than TSMC's, with yields about one third of TSMC'sTrendForce, 28 March 2025, relaying a trade report that itself rested on unnamed industry sources. The weakest link in this table and it should be read as an order-of-magnitude indication, not a measurement[14]
Ascend production plan200,000 Ascend 910B and no 910C in 2024; 300,000 910B and 100,000 910C planned for 2025Financial Times via TrendForce, 25 February 2025[13]
Advanced-node capacityAbout 45,000 wafers per month at the end of 2025, rising to 60,000 in 2026 and 80,000 in 2027SemiAnalysis estimate, 8 September 2025. An earlier SemiAnalysis piece from 16 April 2025 had put SMIC at "nearly 50,000 wafers per month" of advanced capacity during 2025[11][12]

Two cautions apply to that table. First, the 40 percent yield figure is the single most-quoted number in the whole subject and it is the least well specified: it came through the Financial Times from unnamed sources, it describes Huawei's chip programme rather than a SMIC process, and by the time it was published a large fraction of Huawei's Ascend compute dies were not SMIC's at all, as the section below explains. Second, the SemiAnalysis capacity estimates are in 300mm wafers, while SMIC's own disclosures are in 8-inch equivalents. On the standard 2.25 times area conversion, 45,000 300mm wafers per month is about 101,000 8-inch equivalents, which is under a tenth of SMIC's roughly 1.06 million 8-inch-equivalent total at the end of 2025.[2][12] Total capacity and advanced-node capacity are different numbers by an order of magnitude, and treating them as interchangeable is the most common quantitative error in writing about this company.

There is also a strategic reading of the economics that the raw numbers support. SMIC does not have to be profitable at 7nm in the way TSMC is. Its advanced-node line is effectively a state-underwritten strategic asset serving a customer base that has no alternative and is not price-sensitive in the ordinary sense, funded by a mature-node business that is genuinely profitable and by state capital that does not demand a market return. That is a real answer to the cost problem, but it is a financing answer rather than a manufacturing one, and it does not scale to frontier volumes.

United States export controls and the Entity List

SMIC has been a repeated target of American export controls, and the instruments involved are frequently confused with one another. They are separate legal mechanisms with separate consequences.

The Entity List

In September 2020 the Commerce Department notified suppliers that SMIC could be treated as a military end-user, requiring licences before shipping certain equipment. The decisive action followed on 22 December 2020, when the Bureau of Industry and Security published a final rule at 85 FR 83416, document 2020-28031, adding SMIC to the Entity List with an effective date of 18 December 2020.[4]

The entry names "Semiconductor Manufacturing International Corporation (SMIC)" at No. 18 Zhang Jiang Road, Pudong New Area, Shanghai, together with three aliases, and imposes a licence requirement on "All items subject to the EAR." As originally published, the licence review policy read "Presumption of denial for items uniquely required for production of semiconductors at advanced technology nodes (10 nanometers and below, including extreme ultraviolet technology); Case by case for all other items."[4] That text is no longer current. BIS amended SMIC's own entry in the rule of 5 December 2024 at 89 FR 96836, adding a Footnote 5 designation and replacing the policy with a presumption of denial for all items subject to the EAR, including a named list of 3B001, 3B002, 3B993 and 3B994 equipment, with case-by-case treatment now confined to items used to produce 200mm wafers destined for a 200mm production facility.[5] Ten related entities were listed alongside it, including SMIC Beijing, SMIC Tianjin, SMIC Shenzhen, SMIC Holdings, Semiconductor Manufacturing South China, SMIC Northern Integrated Circuit Manufacturing (Beijing), SMIC Hong Kong International, SJ Semiconductor and Ningbo Semiconductor International.[4]

The practical shape of that policy is what defines SMIC's business today. It left the mature-node equipment supply largely intact on a case-by-case basis, which is why the company has been able to grow capacity to more than a million 8-inch equivalents a month, while cutting off the tools most useful below 10nm and permanently foreclosing EUV.

Later rules widened the perimeter. On 13 October 2022, at 87 FR 62186, document 2022-21658, BIS created export control classification number 3B090 and imposed a licence requirement with a presumption of denial on equipment capable of producing logic integrated circuits at 16nm or 14nm and below using non-planar transistors, DRAM at 18nm half-pitch or less, and NAND with 128 or more layers.[27] That rule did not name SMIC, but it converted the company's node-specific restriction into an industry-wide one and cut off the equipment path to anything more advanced than what it already had installed. Then on 5 December 2024, at 89 FR 96830, document 2024-28267 and effective 2 December 2024, BIS added around 140 entities in a single action, including much of SMIC's domestic equipment and materials supply base: NAURA and several regional subsidiaries, Piotech, ACM Research (Shanghai), Shenzhen SiCarrier Technologies, the EDA house Empyrean under its Beijing Huada Jiutian name, Skyverse, SwaySure, Shenzhen Pengxinxu and Wuhan Xinxin, with PXW Semiconductor Manufactory addressed in the modifications section. The rule's stated rationale is that these entities "pose a significant risk of contributing to the efforts of Huawei Technologies Co., Ltd., a party on the Entity List, to support China's government's goal of indigenous production of 'advanced-node ICs' to support its military modernization."[5] The effect on SMIC is both direct and indirect. The same rule amended SMIC's own entry, tightening its review policy to a presumption of denial for all items, and it simultaneously controlled the domestic tools SMIC would need in order to substitute for controlled foreign equipment.

Section 1260H, which is a different instrument

SMIC also appears on the Department of Defense's list of Chinese military companies operating in the United States, maintained under Section 1260H of the FY2021 National Defense Authorization Act. The current notice was published on 10 June 2026 at 91 FR 35189 and names SMIC, noting that it "is indirectly owned by SASAC," alongside CXMT, YMTC and Huawei Investment & Holding.[6]

The two designations do different things. The Entity List is an export-control instrument administered by Commerce: it restricts what American suppliers may ship to SMIC. The 1260H list is a Defense Department transparency and procurement instrument: it identifies companies as Chinese military companies, feeds federal procurement prohibitions and shapes investor and counterparty behaviour, but it does not by itself license or deny an export. A company can be on one and not the other. CXMT, for instance, is on the 1260H list and not on the Entity List, which is part of why it could court foreign customers and list publicly.

Allied measures reinforced the American ones. The Netherlands, home to ASML, began restricting exports of advanced chipmaking equipment in 2023, brought immersion DUV systems into its licensing regime, and tightened the rules again in 2024. By 2025 the pressure had reached design software, with the major electronic design automation vendors instructed to suspend some sales into China.

Role in Huawei's chips

SMIC's most visible role has been as the manufacturing partner that let Huawei's chip design arm HiSilicon return to advanced silicon after American sanctions cut it off from TSMC in 2020. The relationship runs in both directions: reporting through 2025 and 2026 consistently describes Huawei and SMIC working jointly on yield improvement and next-node development rather than as an ordinary foundry and customer.

Kirin

The clearest demonstration came with the Huawei Mate 60 Pro, released on 29 August 2023 and running the HiSilicon Kirin 9000s, a 7nm-class system-on-chip designed and manufactured entirely in mainland China. TechInsights confirmed the SMIC N+2 process by teardown the following month.[7] The launch prompted a Commerce Department review and was widely read as evidence that export controls had not stopped China from producing advanced mobile processors.

Successors followed on the same or an evolved node: the Kirin 9000S1 and Kirin 9010 in the Pura 70 series in 2024, the Kirin 9020 in the Mate 70 series in December 2024, still on N+2 by TechInsights' measurement,[8] and the Kirin 9030 in the Mate 80 series in late 2025, the first product confirmed on N+3.[9][10]

Ascend, and the question of who made the dies

SMIC is routinely described as the manufacturer of Huawei's AI accelerators, and for the current and future generations that is broadly right. For the Ascend 910B and Ascend 910C specifically, the teardown evidence complicates the picture in a way that matters.

The original Ascend 910 was built by TSMC on a 7nm process in 2019. After the 2020 cutoff, Huawei obtained TSMC 7nm compute dies indirectly. The Chinese design house Sophgo submitted Huawei-derived designs to TSMC as though they were its own; TSMC suspended shipments to Sophgo after the compute chiplet it had supplied was identified as part of the HiSilicon Ascend 910 series, and by April 2025 the Commerce Department investigation was reported to be heading toward a penalty of more than a billion dollars, under rules that allow fines of up to twice the value of the offending transactions.[28]

SemiAnalysis, writing on 16 April 2025, stated that "the vast majority of Ascend 910B and 910C are made with TSMC's 7nm" and that "the US Government, TechInsights, and others have acquired Ascend 910B and 910C and every single one used TSMC dies."[11] Its September 2025 follow-up put the scale of the stockpile at more than 2.9 million Ascend dies, usable across both the 910B and the 910C, against shipments of 507,000 Ascend units in 2024, mostly 910B, and 805,000 in 2025 of which 653,000 were 910C, and argued that it was "specifically this 'Die Bank' of foreign chips from TSMC that gets them through 2024 and 2025," with the reserve expected to run out within about nine months of writing.[11][12]

The correct statement, then, is that SMIC has the process capability to build these dies and increasingly does, but that the accelerators fielded in 2024 and 2025 drew heavily on a finite stock of TSMC silicon. This distinction changes how the yield reporting should be read, and it explains why the exhaustion of the die bank in 2026 rather than any node announcement is the event that determines how many Ascends China can build.

Huawei packages large numbers of these accelerators into rack-scale systems such as CloudMatrix 384, the architecture that lets a cluster of individually weaker chips reach competitive aggregate throughput and the reason Chinese labs such as DeepSeek can run inference on domestic silicon at all. TrendForce put the 910C at roughly 800 TFLOPS in FP16 with 3.2 TB/s of memory bandwidth, around 80 percent of an Nvidia H100.[23]

Huawei's forward roadmap, announced on 18 September 2025, runs Ascend 950PR in the first quarter of 2026, 950DT in the fourth quarter of 2026, Ascend 960 in the fourth quarter of 2027 and Ascend 970 in the fourth quarter of 2028, with self-developed high-bandwidth memory starting with the 950 series.[23] Huawei did not name a foundry or a process node for any of them, and no teardown of a 950-series part had been published as of mid-2026. Trade reporting attributing the 950 family to SMIC N+3 should be read as attribution rather than confirmation.

Capacity allocation and China's AI chip designers

For an AI audience this is the most consequential question about SMIC, and it is a question about queueing rather than technology.

Every serious Chinese AI accelerator is fabricated on the same SMIC node. TrendForce's December 2025 assessment listed Cambricon, Biren Technology, Moore Threads, MetaX, Alibaba's T-Head, Baidu's Kunlunxin and Huawei's HiSilicon as "all of whom rely on it to mass-produce their high-end products," referring to N+2.[15] The same analysis noted that "SMIC has limited room to expand output materially, given restrictions on importing critical equipment and spare parts," and concluded that "until SMIC achieves a meaningful breakthrough in both capacity and yields," Cambricon would find a large-scale ramp difficult, against a Bloomberg-sourced plan to ship roughly 500,000 accelerators in 2026 including as many as 300,000 units of the Siyuan 590 and 690.[15]

Who gets those wafers is reported rather than disclosed. The Financial Times reported in August 2025, as relayed by TrendForce, that Huawei was SMIC's largest customer for its advanced processor lines, that SMIC planned to double its 7nm capacity in 2026, and that this expansion "will allow smaller Chinese chipmakers such as Cambricon, MetaX, and Biren to secure larger shares of SMIC's capacity, intensifying competition."[16][17] The same reporting described one fab dedicated to Huawei's AI chips due to start production by the end of 2025 with two more in 2026, part of a plan to triple China's AI processor output during 2026.[16]

The implication is worth stating precisely, because it is easy to overstate. What is well attested is that the advanced-node capacity is finite, that Huawei is the largest customer for it, and that the other designers are competing for what remains. What is not established by any primary source is a specific allocation split; figures circulating in 2026 that assign Huawei a precise percentage of SMIC's advanced capacity trace to unattributed trade posts rather than to reporting or filings, and this article does not repeat them.

The mismatch between that constraint and China's equity markets is the striking part. Moore Threads, MetaX, Biren and Enflame all raised very large sums on the STAR Market and in Hong Kong between late 2025 and mid-2026, at valuations that assume access to advanced wafers; those listings are catalogued in the industry overview linked at the top of this article. Every one of them depends on wafers that a single sanctioned foundry allocates, with the country's largest customer ahead of them in the queue.

There is one further qualification. SemiAnalysis argued in September 2025 that logic wafers were not actually the binding constraint on Huawei's accelerator output at all: it estimated that Ascend production "requires at most 20k wafers per month," a modest share of SMIC's advanced capacity, and that high-bandwidth memory was the real bottleneck, with China having procured about 13 million HBM stacks and CXMT expected to supply only around 2 million more in the following year, enough for perhaps 250,000 to 300,000 additional Ascend 910C packages.[12] If that analysis is right, freeing up N+2 wafers moves the queue rather than clearing it.

Financial performance and capacity

SMIC's reported results reflect both the strength of its mature-node business and the surge in Chinese demand for domestically made chips. All figures below come from the company's own quarterly and annual results releases unless attributed otherwise.

Metric20242025Q1 2026
RevenueUS$8,029.9 million[1]US$9,326.8 million[1][2]US$2,505.5 million[3]
Gross margin18.0%[1]21.0%[1]20.1%[3]
Profit attributable to ownersUS$492.7 million[2]US$685.1 million[1][2]US$197.4 million (TrendForce)[20]
EBITDAUS$4,380 million[1]US$5,256 million[1]n/a
R&D expensen/aUS$774 million, 8.3% of revenue[1]n/a
Capital expendituren/aUS$8.1 billion[2]about US$1.5 billion[20][21]
Monthly capacity, 8-inch equivalentsn/a1,059,000 at year-end[2]1,078,250[20][21]
Capacity utilisationn/a93.5% annualised[1][2]93.1%[20][21]
Wafer shipmentsn/aabout 9.7 million[2]2,509,100[21]

Revenue grew 16.2 percent in 2025 to US$9.33 billion, gross margin improved by three percentage points to 21.0 percent, and profit attributable to owners rose 39.1 percent to US$685.1 million.[1][2] Fourth-quarter 2025 revenue was US$2,488.7 million, up 4.5 percent from US$2,381.8 million in the third quarter, although fourth-quarter gross margin fell to 19.2 percent from 22.0 percent.[2] Capital expenditure was US$8.1 billion for the year, a level comparable to foundries several times SMIC's size, and the company guided 2026 capex to be roughly flat.[2]

First-quarter 2026 revenue was US$2,505.5 million, up 0.7 percent sequentially, with gross profit of US$503.6 million and a gross margin of 20.1 percent.[3] TrendForce reported net profit of US$197.4 million, up about 5 percent year on year but below a consensus of US$223.6 million, and noted that smartphone-related revenue fell to 18.9 percent of the total, the lowest share since 2021.[20] The application mix for the quarter was roughly 46.2 percent consumer electronics, 18.9 percent smartphones, 14.0 percent industrial and automotive and 13.6 percent PCs and tablets, with China accounting for 88.9 percent of sales and the United States 9.3 percent.[20][21] SMIC guided second-quarter 2026 revenue to grow 14 to 16 percent sequentially with a gross margin of 20 to 22 percent, which implies roughly US$2.86 billion to US$2.91 billion.[3]

Two features of these numbers deserve emphasis. First, the growth is overwhelmingly domestic: nearly nine tenths of revenue comes from China, and the demand is being created in significant part by the same export controls that constrain the company's technology, as Chinese customers move away from foreign suppliers. Second, the capacity figures describe the mature-node business almost entirely. Monthly capacity above a million 8-inch equivalents is a statement about display drivers and power-management chips, not about AI accelerators, and the advanced-node fraction of that total is on the order of a tenth once the wafer-size conversion is applied.[12]

Pricing has begun to move. TrendForce reported in January 2026, citing Commercial Times, that SMIC and Hua Hong were operating at full capacity and that prices for certain mature processes had already risen by about 10 percent, driven by demand for power-management components that AI infrastructure build-out consumes in volume.[18]

Recent developments

Through 2025 and into 2026 the story has been the same in outline and steadily larger in scale. Utilisation has stayed above 93 percent, capacity has passed a million 8-inch equivalents a month and kept climbing, mature-node pricing has firmed, and domestic customers have replaced foreign ones.[1][2][18][20]

On the advanced side, the third-generation node moved from confirmed to characterised: TechInsights identified N+3 in the Kirin 9030 in December 2025 and SemiAnalysis published measured dimensions in June 2026, establishing that SMIC had reached TSMC N6 density without EUV and quantifying what it cost in efficiency and process complexity.[9][10] TrendForce's estimate that N+3 and N+4 yields sat near 20 percent at the end of 2025 remains the only public figure of its kind, and there is no published evidence of a 5nm-class node in volume.[15]

The strategic questions for the next two years are all measurable. Whether SMIC's advanced capacity actually doubles as the Financial Times reported it would.[16][17] Whether the Huawei-dedicated fabs come online and shift where Ascend dies are made. Whether Huawei's TSMC die bank exhausts in 2026 as SemiAnalysis expected, forcing genuine reliance on SMIC output.[12] Whether the first domestic immersion scanners qualify on a production line rather than in a test fab.[22] And whether the listed accelerator designers whose valuations assume access to advanced wafers actually receive any.[15] None of these turn on a node announcement, which is the point: SMIC's constraint has not been capability since September 2023. It has been cost, yield and volume.

See also

References

  1. ^SMIC, "SMIC Announces 2025 Annual Results," press release, 26 March 2026. smics.com/...7951
  2. ^SMIC, "SMIC Reports 2025 Fourth Quarter Results," press release, 10 February 2026. smics.com/...7949
  3. ^SMIC, "SMIC Reports 2026 First Quarter Results," press release, 14 May 2026. smics.com/...7956
  4. ^Bureau of Industry and Security, "Addition of Entities to the Entity List, Revision of Entry on the Entity List, and Removal of Entities From the Entity List," Final Rule, 85 FR 83416, published 22 December 2020, effective 18 December 2020, FR Doc. 2020-28031. govinfo.gov/...2020-28031
  5. ^Bureau of Industry and Security, "Additions and Modifications to the Entity List; Removals From the Validated End-User (VEU) Program," Final Rule, 89 FR 96830, published 5 December 2024, effective 2 December 2024, FR Doc. 2024-28267. govinfo.gov/...2024-28267
  6. ^Department of Defense, "Notice of Availability of Designation of Chinese Military Companies," 91 FR 35189, 10 June 2026. govinfo.gov/...2026-11571
  7. ^TechInsights, "TechInsights finds SMIC 7nm (N+2) in Huawei Mate 60 Pro," September 2023. techinsights.com/...smic-7nm-n2-huawei-mate-60-pro
  8. ^TechInsights, "Huawei Mate 70 Pro+: Exploring the HiSilicon Kirin 9020 Processor," December 2024. techinsights.com/...hisilicon-kirin-9020-processor
  9. ^TechInsights, "SMIC N+3 Confirmed: Kirin 9030 Analysis Reveals How Close SMIC is to 5nm," 11 December 2025. techinsights.com/...sis-reveals-how-close-smic-5nm
  10. ^SemiAnalysis, "STEEL: SMIC N+3 Teardown," 14 June 2026. newsletter.semianalysis.com/...el-smic-n3-teardown
  11. ^SemiAnalysis, "Huawei AI CloudMatrix 384: China's Answer to Nvidia GB200 NVL72," 16 April 2025. newsletter.semianalysis.com/...-nvidia-gb200-nvl72
  12. ^SemiAnalysis, "Huawei Ascend Production Ramp: Die Banks, TSMC Continued Production, HBM is The Bottleneck," 8 September 2025. newsletter.semianalysis.com/...end-production-ramp
  13. ^TrendForce, "China Advances in AI Chips: Huawei Reportedly Boosts Yield to 40%, Making Ascend Line Profitable," 25 February 2025. trendforce.com/...40-making-ascend-line-profitable
  14. ^TrendForce, "SMIC Reported to Complete 5nm Chips by 2025, But Costs May Be 50% Higher Than TSMC's," 28 March 2025. trendforce.com/...osts-may-be-50-higher-than-tsmcs
  15. ^TrendForce, "[Insights] Cambricon Remains China's Top AI Chip Startup; Rumored 2026 Triple Output Faces SMIC Limits," 15 December 2025. trendforce.com/...-triple-output-faces-smic-limits
  16. ^TrendForce, "China Reportedly to Triple AI Chip Output Next Year, with Fabs Serving Huawei, Cutting NVIDIA Reliance," 28 August 2025. trendforce.com/...g-huawei-cutting-nvidia-reliance
  17. ^TrendForce, "SMIC 1H25 Net Profit Rises 35.6%, 7nm Capacity Reportedly to Double in 2026," 29 August 2025. trendforce.com/...ity-reportedly-to-double-in-2026
  18. ^TrendForce, "AI Demand to Lift Mature-Node Prices: SMIC Reportedly Up 10%, Vanguard Estimated Up 4-8% from Q1," 27 January 2026. trendforce.com/...anguard-estimated-up-4-8-from-q1
  19. ^TrendForce, "Global Top 10 Foundries' Revenue, 1Q26," press release, 12 June 2026. trendforce.com/...20260612-13095
  20. ^TrendForce, "SMIC Q1 Net Profit Up 5%, Misses Forecasts; Smartphone-Related Revenue Share Hits Lowest Since 2021," 15 May 2026. trendforce.com/...nue-share-hits-lowest-since-2021
  21. ^China Business Insider, "SMIC Raises Full-Year Outlook as Domestic Orders Drive Q2 Guidance Well Above Consensus," May 2026. chinabizinsider.com/...idance-well-above-consensus
  22. ^Asia Times, "China's DUV lithography still lags ASML by four generations," July 2026. asiatimes.com/...ill-lags-asml-by-four-generations
  23. ^TrendForce, "Huawei Unveils Ascend 950 with In-House HBM in 2026, Touts SuperPoD to Rival NVIDIA," 18 September 2025. trendforce.com/...6-touts-superpod-to-rival-nvidia
  24. ^SMIC, "SMIC Reports 2019 Fourth Quarter Results," press release, 13 February 2020. prnewswire.com/...fourth-quarter-results-301004422
  25. ^TSMC, "TSMC and SMIC Reach Settlement," press release, 10 November 2009. pr.tsmc.com/...1586
  26. ^TrendForce, "China's DRAM Maker CXMT to Debut Jul 27, IPO to Raise RMB 57.9B, Largest on STAR Market Since Launch," 24 July 2026. trendforce.com/...gest-on-star-market-since-launch
  27. ^Bureau of Industry and Security, "Implementation of Additional Export Controls: Certain Advanced Computing and Semiconductor Manufacturing Items; Supercomputer and Semiconductor End Use; Entity List Modification," 87 FR 62186, 13 October 2022, FR Doc. 2022-21658. govinfo.gov/...2022-21658
  28. ^TechSpot, "TSMC faces $1 billion US fine over chip that ended up in Huawei AI processor," 9 April 2025. techspot.com/...-faces-1-billion-us-fine-over-chip

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Reviewer note: Independently fact-checked on 2026-08-01. The node evidence tiers, the SemiAnalysis Kirin 9030 Pro measurements, the capacity arithmetic separating advanced-node from total 8-inch-equivalent output, and the finding that no published teardown shows an SMIC 5nm-class retail product all held. The correction that most examined Ascend 910B and 910C dies are TSMC parts from the Sophgo die bank was confirmed against SemiAnalysis and is not overstated. Five corrections were applied, the most significant being that the Entity List review policy was quoted from the 2020 text when BIS amended SMIC's entry in December 2024 to a presumption of denial for all items, and that a direct quotation attributed to SemiAnalysis did not appear in the source.

Cite this page: AI Wiki. "SMIC." aiwiki.ai, updated 1 Aug 2026, fact-checked 1 Aug 2026. CC BY 4.0. https://aiwiki.ai/wiki/smic

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