Zettascale Computing
Zettascale Computing (Zettascale Computing Corp., or "zscc" for short, in the company's own usage) is a San Francisco startup that designs reconfigurable AI chips it calls XPUs. Led by founder and chief executive Elias Almqvist, it was founded in 2024 as Exa Laboratories, went through Y Combinator's Summer 2024 batch, and adopted its current name in September 2025.[1][2][3] The site footer states that "Zettascale is a DBA of Exa Laboratories, Inc."[4] On 7 October 2026 the company announced XPU Grasshopper, an architecture it says was co-designed with autonomous AI agents and that ran Gemma 3 1B end to end on an FPGA, and opened pre-orders for a limited run of 100 FPGA development kits scheduled to ship in February 2027.[5][4][6]
The company describes its product as "AI silicon for recursive self-improvement and superintelligence" and says its chips will "run inference and training for frontier AI models on a fraction of the energy."[4] As of October 2026 its architecture runs on FPGA prototypes, and its published timeline lists the tapeout of Gen 1 silicon as a later step.[4][5] (The general term "zettascale computing" also refers to computers that perform on the order of 10^21 operations per second; this article covers the company.)
History
Exa Laboratories (2024 to 2025)
Exa Laboratories made its Launch YC post on 27 August 2024. It introduced two founders: chief executive Elias Almqvist, described as a self-taught engineer who studied computer science and computer engineering at Chalmers University of Technology before dropping out to found the company, and chief technology officer Prithvi Raj, who holds an MEng from the University of Cambridge's Computational Statistics and Machine Learning lab and had interned at Microsoft.[2] The post pitched "reconfigurable chips for AI" and said early simulations indicated potential efficiency gains of up to 27.6x over the NVIDIA H100.[2]
TechCrunch reporter Marina Temkin listed Exa Laboratories among nine startups that stood out at the second Demo Day of the Summer 2024 batch (26 September 2024). The piece noted that early tests "purportedly" showed the chips to be nearly 28 times more efficient than H100s, and that Exa hoped to have them ready for use by early 2025.[7]
According to the company, it raised a seed round in September 2024, which it described as "a good couple of million dollars," and said a year later that it had been "quiet for almost a year now, heads down building."[3] Its team page names Y Combinator, Olive Tree Capital and Soma Capital as backers, "and others."[8]
Rename to Zettascale (September 2025)
On 4 September 2025 the company announced that "Exa Laboratories" was now the "Zettascale Computing Corporation." It said exascale computing was "no longer ambitious enough, due to recent internal breakthroughs," and that its goal had shifted from "making the ExaFLOP sustainable" to "making Zettascale computing sustainable."[3] The announcement was PGP-signed with both the old Exa key and a new key for the zscc.ai domain.[3]
Team
Y Combinator's company page lists the company as founded in 2024, with a team size of two, Tom Blomfield as primary partner, and Almqvist (Founder/CEO) as its active founder.[1] The company's own team page lists Almqvist and a founding silicon engineer, Ezra Wolf, and says the company is "a small, deeply technical founding team, in person in San Francisco" that intends to stay small.[8] In October 2026 it was hiring a founding silicon engineer at a listed salary of US$200,000 to US$300,000.[1][9]
Early design: the Learnable Function Unit
Exa's 2024 litepaper, which the company later labeled "Litepaper of the old chip architecture," described a "polymorphic" architecture built from Learnable Function Units (LFUs). Each LFU was a hardware block that approximates a configurable univariate function at FP32 precision; networks of LFUs were meant to implement multilayer perceptrons, Kolmogorov-Arnold Networks and transformer components.[10] The paper defined a theoretical property it called "Exa completeness," inspired by the Kolmogorov-Arnold representation theorem.[10]
The 27.6x figure came from this paper. Simulations of LFU revision 0.4.1 gave 2,362 GFLOPS/W (FP32) at 400 W, compared with about 85.7 GFLOPS/W that the paper attributed to the H100 at a 700 W TDP. The paper stated that the simulations covered individual LFU cores only, excluded the power of the interconnect network, and were "preliminary" and "subject to revision."[10]
| LFU revision | Max LFU power | LFU cores | Max power | Max FP32 performance | FP32 efficiency |
|---|---|---|---|---|---|
| 0.1 | 2.04 mW | 196 K | 400 W | 19.6 TFLOPS | 49.02 GFLOPS/W |
| 0.4 | 231 µW | 1.73 M | 400 W | 519 TFLOPS | 1,298 GFLOPS/W |
| 0.4.1 | 127 µW | 3.14 M | 400 W | 945 TFLOPS | 2,362 GFLOPS/W |
Simulated figures from the Exa Laboratories litepaper (27 August 2024).[10]
XPU Grasshopper
Announcement
Almqvist announced XPU Grasshopper on X on 7 October 2026 as "an AI chip co-designed with AI for the era of recursive self-improvement," adding that "it went from its first tokens to 816x faster in 13 weeks."[6] The company published a detailed write-up (dated as written on 22 September and published on 7 October 2026) and a Launch YC post the same day.[5][11] The company says the name is inspired by the SpaceX Grasshopper test rocket, and it calls XPU Grasshopper "that first hop for polymorphic computing."[5]
Architecture
Grasshopper is a mesh of Mutation Tile Units (MTUs). Each MTU has its own scratchpad memory next to its compute, and DRAM sits at the edges of the mesh. The company's design rationale is that moving data costs far more energy than arithmetic, so the data should stay close to the math.[5] It says the dataflow "reconfigures for each model instead of freezing one paradigm into silicon," and that the design is simple enough for AI agents to program.[5][4]
The benchmarked build is four MTUs in a 2x2 mesh on an AMD VU47P FPGA, a member of AMD's Virtex UltraScale+ HBM family.[5][12] The company also published the planned Gen 1 silicon design, which it describes as the same architecture with 196 tiles.[5]
| XPU Grasshopper (VU47P), FPGA build | Gen 1 silicon (design) | |
|---|---|---|
| Tiles (MTUs) | 4, 2x2 mesh | 196, 14x14 mesh |
| Compute per tile | 28.8 GOPS INT8 | 2.05 TOPS INT8 |
| Total compute | 115 GOPS INT8 | 401 TOPS INT8 |
| On-chip memory | 512 KiB BRAM per MTU, 2 MiB total | 2 MiB SRAM per MTU, 392 MiB total |
| DRAM | 16 GB, 4 ports | 48 GB |
| Host interconnect | PCIe 4.0 x8 | PCIe x16, QSFP-DD |
| Clock | 225 MHz | 1 GHz or higher |
| Device or process | AMD VU47P FPGA | TSMC N7 |
Company-published figures.[5] AMD lists the VU47P as a 16 nm Virtex UltraScale+ HBM device with 16 GB of in-package HBM2 memory.[12]
AI co-design loop
The company says a handful of engineers worked with autonomous AI agents that rewrote kernels, reworked the hardware overlay, scheduled and ran FPGA builds, and tested each new image on the full model, keeping whatever made the model faster.[5] All measurements were on gemma-3-1b-it at INT8 and batch size 1, and each data point is the best run of that day.[5]
| Date (2026) | Milestone, as reported by Zettascale |
|---|---|
| 30 June | First tokens, on a single tile, at 0.06 tokens per second |
| 19 August | First run on the 2x2 mesh with DRAM online |
| 7 September | AI agent finds a hardware optimization: 12 to 21 tok/s |
| 8 September | AI kernel optimizations on that image: 21 to 25 tok/s |
| 14 September | A second hardware optimization: 28 to 35 tok/s |
| 14 September to 2 October | Continued loop: 35 to 51 tok/s |
Source: Zettascale announcement.[5]
The company states that its engineers "set the targets and the architecture," while within those limits "the AI proposed these changes, built them, measured them, and kept the ones that made the model faster." It calls this "an early form of recursive self-improvement, with AI improving the hardware that AI runs on."[5] The 816x figure compares the 2 October result with the company's own first run on 30 June; it is not a comparison with other hardware.[5]
Benchmark claims
Zettascale reports that on 2 October 2026 the VU47P build ran gemma-3-1b-it at 51.0 tokens per second at INT8, reading 1.0 GB per token, which it calculates as 89% of the build's peak memory bandwidth (memory bandwidth utilization, or MBU). It also reports a time to first token of about 180 ms and FPGA core power of about 21 W, measured on the VCCINT rail only and excluding other board rails, regulator losses and host power.[5]
For comparison, the company cites 41.3 tok/s for the same model on an NVIDIA Jetson Orin Nano Super, using a Q4_K_M quantization in llama.cpp at 25 W, which it took from a public benchmark published by Yuvraj Singh in May 2026. It gives the Jetson an MBU of 33%. Both runs used a 128-token prompt and 256 generated tokens and report the median of 20 requests.[5][13] The two systems ran different quantization formats (INT8 against Q4_K_M), and the comparison is the company's own.
XPU Grasshopper (KU040) devkit
The devkit is a PCIe card carrying two AMD Kintex UltraScale XCKU040 FPGAs linked by SerDes, configured to run the Grasshopper 2x2 mesh. The company says it can also be used as an ordinary FPGA board, and that it is meant "for building on the new architecture today" and "not meant for production serving."[4] The product page calls it "the Gen 1 architecture on your desk, before silicon," while its specification table lists the edition as "Gen0."[4] The published benchmark was run on the in-house VU47P build, not on this card; the company says the KU040 board "runs the same 2x2 mesh as the benchmarked VU47P version."[4][5]
| Item | Specification (company-published) |
|---|---|
| Architecture | Grasshopper 2x2, 4 MTUs |
| FPGAs | 2x AMD Kintex UltraScale XCKU040, linked by SerDes |
| Process | 20 nm |
| Logic cells | 1,060,500 (both FPGAs) |
| DSP slices | 3,840 (both FPGAs) |
| Block RAM | 42.2 Mb (both FPGAs) |
| Host interface | PCIe Gen3 x8 |
| Interconnect | QSFP-DD, degree 4 |
| Software | Open-source runtime, driver and libxpu |
| Edition | Limited edition, Gen0, numbered 1 to 100 |
Source: XPU Grasshopper product page.[4] The FPGA totals are consistent with twice AMD's per-device figures for the XCKU040 (listed as 530K system logic cells, 1,920 DSP slices and 21.1 Mb of block RAM), and AMD describes the Kintex UltraScale family as 20 nm devices.[14]
Pricing and availability
Pre-orders opened on 7 October 2026 at US$9,599, 20% below the US$11,999 list price, with a US$960 deposit that the company says is fully refundable until the board ships. The balance is due when the board is ready to ship.[4] The company gives a ship date of 1 February 2027, which it says may move because of component supply or manufacturing delays. Prices exclude tax and shipping, and boards ship within the United States only.[4] Pre-order buyers are placed in "batch #0" for early API and SSH access to the company's FPGA cluster.[4] Enterprise and cluster inquiries are handled separately and, according to the company, are for Gen 1 silicon rather than the devkit.[4]
Software
Zettascale says the stack above the hardware will ship as open source, including the runtime, the driver and libxpu, which it describes as "a C ABI over the whole machine."[4][15] Following what it calls "the UNIX tradition," the runtime exposes each card as a device file at /dev/xpu/N. A kernel is a single binary holding every MTU's program and the locations of its inputs and outputs; the host writes the kernel and inputs, triggers execution, polls a status register and reads the outputs, and the company states that kernels are fully deterministic.[4] Kernels can be written ahead of time or just in time, "in any language," by a person, a compiler or an AI.[4]
The company positions frameworks and engines such as PyTorch, tinygrad, JAX, Ollama and vLLM as the layer above the kernel interface.[4] Its homepage also advertises "XPU Frontends" for PyTorch, tinygrad and JAX, offered as early access, with a code sample that moves a PyTorch model to an "xpu" device.[15] The homepage describes libxpu as "planned to be fully open source."[15]
Roadmap and Monolith
The product page sets out the company's planned sequence: in-house end-to-end inference on the VU47P FPGA, an XPU FPGA cluster with a serving API, the KU040 devkit, Gen 1 silicon tapeout, and finally Monolith, which it calls a "frontier AI computer."[4] Monolith is described as many XPUs connected into "one machine that behaves as one chip," running agents, experience generation and training on the same silicon. The company says it will be hosted and rolled out in batches, and marked it "Soon" as of October 2026.[4][16]
Thesis
In an essay titled "The Final Frontier of Intelligence" (1 June 2026, updated 8 July 2026), the company argues that "AI is not a bubble, LLMs are": text data is nearly exhausted, future progress will come from models learning from experience they generate, and most of that compute will go to generating rollouts.[17] It places existing chips on a spectrum from FPGAs (flexible but slow at heavy math) through GPUs and TPUs to ASICs (fast but fixed), and argues that the target workload combines dense low-precision math, sparsity and long-lived state. It describes the range it is aiming for as the "lagom" between a GPU and a TPU.[17] The company's product page summarizes the positioning as "GPUs were made for graphics. TPUs for matmuls. XPUs for frontier AI."[4] Its homepage extends the long-term vision to an "AI Discovery Factory" and, eventually, a Dyson swarm around the Sun.[15]
References
- ^1 ^2 ^3Y Combinator. "Zettascale Computing: Chips for frontier AI." Company directory. ycombinator.com/...zettascale-computing (accessed 15 October 2026).
- ^1 ^2 ^3Exa Laboratories. "Exa Laboratories - 27.6x more efficient chips for AI." Launch YC, 27 August 2024. ycombinator.com/...-6x-more-efficient-chips-for-ai
- ^1 ^2 ^3 ^4Zettascale Computing. "Announcing our new name, Zettascale, & progress." 4 September 2025. zscc.ai/zetta
- ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8 ^9 ^10 ^11 ^12 ^13 ^14 ^15 ^16 ^17 ^18 ^19 ^20Zettascale Computing. "XPU Grasshopper." Product page. zscc.ai/grasshopper (accessed 15 October 2026).
- ^1 ^2 ^3 ^4 ^5 ^6 ^7 ^8 ^9 ^10 ^11 ^12 ^13 ^14 ^15 ^16 ^17Zettascale Computing. "Introducing XPU Grasshopper, an AI chip co-designed with AI for the era of recursive self-improvement." 7 October 2026. zscc.ai/announcing-xpu-grasshopper
- ^1 ^2Almqvist, Elias (@fcvprzhfgsybj). Post on X announcing XPU Grasshopper, 7 October 2026. x.com/...2107863478560251945
- ^Temkin, Marina. "9 startups that stood out on YC Demo Day 2." TechCrunch, 26 September 2024. techcrunch.com/...-that-stood-out-on-yc-demo-day-2
- ^1 ^2Zettascale Computing. "Team." zscc.ai/team (accessed 15 October 2026).
- ^Zettascale Computing. "Careers." zscc.ai/careers (accessed 15 October 2026).
- ^1 ^2 ^3 ^4Exa Laboratories. "Litepaper: Exa, the next paradigm of sustainable hardware for AI." 27 August 2024. Archived copy: web.archive.org/...litepaper
- ^Zettascale Computing. "XPU Grasshopper: An AI chip designed for the era of recursive self-improvement." Launch YC, 7 October 2026. ycombinator.com/...a-of-recursive-self-improvement
- ^1 ^2AMD. "AMD Virtex UltraScale+ HBM FPGAs." amd.com/...virtex-ultrascale-plus-hbm (accessed 15 October 2026).
- ^Singh, Yuvraj. "Tiny LLM Benchmark: Jetson Orin Nano Super 8GB." 29 May 2026. yuvrajsingh.io/...no-super-benchmark-non-reasoning
- ^AMD. "AMD Kintex UltraScale FPGAs." amd.com/...kintex-ultrascale (accessed 15 October 2026).
- ^1 ^2 ^3 ^4Zettascale Computing. Homepage. zscc.ai (accessed 15 October 2026).
- ^Zettascale Computing. "Monolith." zscc.ai/monolith (accessed 15 October 2026).
- ^1 ^2Zettascale Computing. "The Final Frontier of Intelligence." 1 June 2026, updated 8 July 2026. zscc.ai/the-final-frontier
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