FPGA

A field-programmable gate array (FPGA) is an integrated circuit whose logic functions and internal wiring are set by the customer after the chip has been manufactured, and can be reset later. Instead of the fixed datapath of a CPU or a GPU, an FPGA presents a blank fabric of small programmable logic elements, storage bits, arithmetic blocks, and configurable routing. A design compiled from a hardware description language becomes a bitstream that configures every one of those elements, so the chip physically implements the circuit the designer drew rather than interpreting instructions that describe it.

The category dates to 1985, when Xilinx shipped the XC2064. The company's co-founder Ross Freeman is credited with the invention, and the bet behind it was that Moore's law would make transistors cheap enough that leaving many of them idle was an acceptable price for programmability ^[1]. The XC2064 held 64 configurable logic blocks in an 8x8 grid, each built from two 3-input lookup tables and a flip-flop, with the configuration stored in a 160 by 71 array of SRAM cells loaded from an external bitstream at power-up through a shift register running down the middle of the die ^[2]. Forty years later the largest parts hold millions of equivalent logic cells, hardened Arm processors, PCIe and Ethernet controllers, and thousands of arithmetic blocks ^[33], but the SRAM-configured principle is unchanged.

FPGAs occupy an awkward middle ground in AI hardware. They are more flexible than an ASIC and far cheaper to bring up, since there is no mask set and no non-recurring engineering charge for a new design. They are also markedly less efficient than an ASIC per unit of work, and they lost the mainstream deep learning inference market to GPUs and purpose-built accelerators. Where they remain strong is at the extremes: single-digit-microsecond and sub-microsecond latency, unusual numeric formats, tight power budgets at the edge, and workloads where the surrounding I/O matters as much as the arithmetic.

Architecture

The fabric is a two-dimensional array of programmable logic tiles embedded in a programmable routing network, with columns of hardened blocks interleaved. The basic building block is the lookup table (LUT), a small memory whose contents define a truth table. A six-input LUT is 64 bits of configuration memory that can realize any Boolean function of six variables.

AMD's UltraScale devices place one slice in each configurable logic block, containing eight 6-input LUTs and sixteen flip-flops. A slice can be a SLICEL, which supplies logic, carry chains, and wide multiplexers, or a SLICEM, which additionally lets its LUTs act as distributed memory or shift registers. In SLICEM mode a single LUT becomes a 64x1 or 32x2 RAM, and the eight LUTs combine into memories of up to 512 bits ^[3]. Altera organizes the equivalent resources differently. In its Agilex 5 devices the basic building block is the adaptive logic module (ALM), and ALMs are grouped into logic array blocks that can be configured to implement logic functions, arithmetic functions, and register functions ^[37].

Dedicated blocks handle the work that would waste fabric. On-chip memory in UltraScale devices comes as 36 Kbit block RAMs, each usable as one 36 Kbit RAM or two independent 18 Kbit RAMs, plus UltraRAM blocks storing 288 Kbit each and arranged as 4K x 72 ^[4][5]. Arithmetic runs on DSP slices: the UltraScale DSP48E2 combines a 27-bit pre-adder, a 27 x 18 two's complement multiplier, and a 48-bit accumulator and logic unit, widened from the 25 x 18 multiplier of the previous generation ^[6]. AMD's Versal devices carry a DSP58, which keeps the 27-bit pre-adder, widens the multiplier to 27 x 24 and the logic unit to 58 bits, and adds floating-point, complex-arithmetic, and dot-product units ^[38]. Chaining many DSP slices through their cascade paths is how an FPGA builds a systolic array or a matrix multiplication engine.

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Routing consumes most of the die area and most of the timing budget. A signal crossing the chip passes through many programmable interconnect points, each a pass transistor controlled by a configuration bit, and each adding resistance and capacitance. This is the structural reason FPGAs clock far slower than ASICs built on the same process. In the most careful measurement of the gap, the critical path delay of an FPGA implementation was roughly 3 to 4 times that of the same circuit in 90 nm standard cells ^[16].

Design flow and toolchains

The conventional flow starts with a register-transfer-level description in Verilog, SystemVerilog, or VHDL. Synthesis maps that description onto LUTs, flip-flops, and hard blocks; placement assigns each element to a physical site; routing commits every net to specific wires and switches; and static timing analysis confirms that every path meets its clock constraint. The result is a bitstream. Compile times for a large design are measured in hours rather than seconds, and that gap is the single biggest practical difference from software development.

High-level synthesis (HLS) exists to shorten that loop. Xilinx acquired AutoESL Design Technologies in January 2011 for its AutoPilot tool, which accepts C, C++, or SystemC and intelligently generates register transfer level code meeting performance, power, area, and timing objectives ^[7]. AMD's C and C++ to RTL synthesis product today is Vitis HLS, which feeds both the Vivado IP flow and the Vitis application acceleration flow ^[41]. HLS raises the abstraction level but does not remove the need to think in hardware: throughput still depends on how the designer pipelines loops, partitions arrays across block RAMs, and manages off-chip bandwidth.

Vendor tools are proprietary, and the bitstream formats were long undocumented. Open-source flows grew out of reverse engineering. Project IceStorm set out to document the bitstream format of Lattice iCE40 FPGAs and to provide tools for analyzing and creating bitstream files ^[8]. Chained with the Yosys synthesis suite and the vendor-neutral nextpnr place-and-route tool, its icepack utility completes a Verilog-to-bitstream path that touches no vendor software at any stage ^[40].

Partial reconfiguration is a capability with no analogue in fixed-function silicon. AMD's Dynamic Function eXchange allows the reconfiguration of modules within an active design, loading a partial bitstream for one region while the rest of the device carries on ^[9]. A data center card can therefore swap an accelerator kernel without a reboot, which is what makes an FPGA a plausible multi-tenant resource.

Vendors and industry structure

Two suppliers dominate the high end, and both have changed owners in the last decade.

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Altera's revenue illustrates how cyclical the business is: $1.54 billion in fiscal 2024, against roughly $2.9 billion in 2023, before returning to growth under independent ownership ^[12][14]. AMD's Embedded segment, which houses the former Xilinx product lines, generated $3.454 billion in 2025, down 3% year over year, while the company's Data Center segment reached $16.635 billion ^[15]. The Embedded segment also carries non-FPGA products, so it overstates programmable logic revenue, but the comparison sets the scale: inside the company that owns the largest FPGA franchise, that franchise sits at roughly a fifth of the data center business.

Tradeoffs against GPUs and ASICs

The clearest quantitative account of the FPGA-to-ASIC gap remains a 2006 study by Ian Kuon and Jonathan Rose, which compared a 90 nm FPGA against 90 nm standard-cell ASICs on the same benchmark circuits. For designs using only combinational logic and flip-flops the FPGA needed on average 40 times the silicon area; hard blocks such as multipliers and block memories cut that average gap to as little as 21. Critical path delay was roughly 3 to 4 times longer, and dynamic power consumption about 12 times higher ^[16]. Process nodes have moved on, but the ratios come from programmability itself and have not fundamentally changed.

Against that, an ASIC carries mask and design costs that must be committed before a single chip works, and a fixed function that cannot be revised once taped out. The FPGA trade is straightforward: pay a large per-unit efficiency penalty in exchange for zero non-recurring engineering cost, weeks instead of years to a working system, and the ability to change the hardware after deployment.

Against GPUs the comparison is different again. A GPU is fixed hardware with an enormous software ecosystem and very high memory bandwidth; an FPGA is malleable hardware with modest bandwidth and a much smaller ecosystem. FPGAs win on determinism, because a hand-built pipeline has a fixed cycle count with no caches, no schedulers, and no batching, and they win when the numeric format is unusual, since a GPU can only run the precisions its tensor units implement while an FPGA can build a 3-bit or 5-bit datapath if that is what the model needs.

FPGAs in AI systems

The most consequential deployment was Microsoft's. Project Catapult put one Altera Stratix V D5 FPGA with 8 GB of DDR3 on a daughtercard in each of 1,632 servers, wired into 6x8 two-dimensional tori across half-racks of 48 machines and drawing under 25 W per board. Offloading part of Bing's ranking stack onto groups of eight FPGAs improved ranking throughput per server by 95% at a fixed latency distribution, or cut tail latency by 29% at equivalent throughput ^[17]. The follow-on architecture moved the FPGA between the network switch and the server NIC, letting FPGAs talk to each other directly and be pooled independently of the hosts they sit in; Microsoft reported average round-trip latencies under 3, 9, and 20 microseconds across 24, 1,000, and 250,000 machines respectively ^[18].

That fabric then served two very different purposes. Project Brainwave, unveiled at Hot Chips in August 2017, synthesized a soft DNN processing unit onto Intel's 14 nm Stratix 10 FPGAs and ran it in a custom 8-bit floating point format Microsoft called ms-fp8, serving requests with no batching at all. On a large gated recurrent unit model, five times the size of ResNet-50, Microsoft reported 39.5 teraflops with each request running in under one millisecond ^[19][20]. Separately, the same class of hardware became Azure's network offload: AccelNet used FPGA-based SmartNICs deployed on all new Azure servers from late 2015 across a fleet of more than one million hosts, delivering consistent sub-15-microsecond VM-to-VM TCP latency at 32 Gbps ^[21]. Measured by units shipped, network acceleration has been by far the larger FPGA workload inside Microsoft.

Cloud providers also rented FPGAs directly. AWS previewed EC2 F1 instances on 30 November 2016, with one to eight Xilinx UltraScale+ VU9P devices per instance, each with roughly 2.5 million logic elements, about 6,800 DSP engines, and 64 GiB of ECC DDR4, programmed in VHDL or Verilog through Vivado ^[22]. The second generation, F2, carries up to eight AMD Virtex UltraScale+ HBM VU47P FPGAs with 16 GB of high-bandwidth memory per device, and AWS claims up to 60% better price performance than F1 ^[23]. Azure's NP-series virtual machines expose AMD Alveo U250 cards with 64 GB each for inference, video transcoding, and database search and analytics, but Microsoft has scheduled the series for retirement on 31 May 2027 and points migrating customers at GPU instance families instead ^[24].

Research toolchains showed what the fabric could do at the low-precision extreme. FINN, from Xilinx Research Labs, built streaming accelerators for binarized neural networks and reported 12.3 million MNIST classifications per second at 0.31 microseconds of latency, and 21,906 classifications per second at 283 microseconds on CIFAR-10 and SVHN, on a ZC706 board under 25 W of system power ^[25]. In physics, the hls4ml package compiles trained networks into FPGA firmware for the Large Hadron Collider trigger, where a jet-substructure classifier ran with latency on the order of 100 nanoseconds, inside the sub-microsecond budget the trigger allows ^[26]. Both vendors now ship production toolchains for the same purpose: AMD's Vitis AI takes TensorFlow and PyTorch models and targets the DPU, a programmable engine optimized for deep neural networks that is integrated into the device's programmable logic alongside the rest of the design ^[35], and Altera's FPGA AI Suite consumes OpenVINO model representations and generates inference IP for Agilex 3, Agilex 5, and Agilex 7 devices, in both host-attached and standalone configurations ^[36].

Why FPGAs did not win mainstream inference

The honest answer was written by FPGA advocates. Intel's own 2017 paper arguing that FPGAs might overtake GPUs opened by conceding the state of play: "Current FPGAs offer superior energy efficiency (Ops/Watt), but they do not offer the performance of today's GPUs on DNNs" ^[27]. Its case rested on a bet that mainstream models would move toward pruning, sparsity, and 1-2 bit weights, patterns that map badly to fixed GPU datapaths and well to custom logic. On Stratix 10 the authors projected 10%, 50%, and 5.4x better GEMM throughput than a Titan X Pascal for pruned, Int6, and binarized networks, and 60% better performance with 2.3x better performance per watt on Ternary ResNet ^[27].

That bet did not pay off at scale, for several reinforcing reasons. Dense low-precision arithmetic won instead of extreme quantization, and GPU vendors hardened exactly those formats into tensor units, erasing the FPGA's customization advantage on the operations that matter most. Memory bandwidth and dense throughput diverged: NVIDIA's specification sheet for the H100 SXM lists 3.35 TB/s of memory bandwidth and 3,958 INT8 tensor-core TOPS with sparsity, neither of which any FPGA of that era approached ^[28]. The efficiency penalty measured by Kuon and Rose meant that any workload stable enough to justify custom silicon eventually got custom silicon, which is what Google did with the TPU and what Microsoft itself did with the Maia 100 accelerator built on a 5 nm TSMC node ^[29]. And the software gap never closed: a model that runs on a GPU the day it is published may need weeks of hardware engineering and a multi-hour place-and-route to run on an FPGA at all.

Other applications

FPGA revenue has never depended on AI. A major use is pre-silicon verification, where FPGA-based prototyping systems run a chip design before tapeout: Cadence's Protium X3, announced on 17 April 2024, incorporates the AMD Versal Premium VP1902 adaptive SoC and, with its Palladium Z3 emulation counterpart, scales from job sizes of 16 million gates up to 48 billion gates ^[30]. Wireless base stations, aerospace and defense radar and signal processing, industrial control, medical imaging, video broadcast, and automotive sensor fusion are all long-standing markets, and they favor FPGAs for the same reasons: long product lifetimes, evolving standards, hard real-time deadlines, and volumes too low to amortize an ASIC.

Electronic trading is the purest latency case. AMD's Alveo UL3524, announced on 27 September 2023, is a custom 16 nm Virtex UltraScale+ device built for trade execution, with 64 ultra-low-latency transceivers, 780,000 LUTs, 1,680 DSP slices, and FPGA transceiver latency under 3 nanoseconds, which AMD describes as a sevenfold latency improvement over prior generation FPGA technology ^[34]. At those timescales no software stack competes, because a network round trip through an operating system kernel costs more than the entire FPGA decision path.

Recent developments

Altera has been rebuilding as an independent company. At Embedded World in March 2025 it opened ordering for production-quality parts in the low-power, cost-optimized Agilex 3 family, released the first Agilex 5 E-Series devices for high-volume production, and added variable pitch BGA packages to the MAX 10 line, aimed at robotics, factory automation, and medical edge systems, with FPGA AI Suite release 25.1 supporting AI inference development on both Agilex 3 and Agilex 5 ^[31]. On 8 June 2026, at the International Microwave Symposium, it announced engineering sample availability of the next-generation wideband Agilex 9 Direct RF-Series, which combines high-speed data converters, programmable logic, and processing elements in one package for aerospace, defense, and advanced communications, with production silicon and development kits scheduled for the third quarter of 2026 ^[32]. By mid-2026 CEO Raghib Hussain described Altera as growing again and preparing for a possible IPO, and positioned FPGAs as complementary to GPUs rather than competitive with them, saying that if the GPU is the brain, the FPGA is the nervous system ^[14].

AMD's roadmap points the same way. Versal Premium Series Gen 2, announced in November 2024, pairs up to about 3.27 million system logic cells with dual Arm Cortex-A72 and Cortex-R5F cores, PCIe Gen6, CXL 3.1, and DDR5 and LPDDR5X interfaces, with samples in early 2026 and production in the second half of 2026 ^[33]. The emphasis in both roadmaps is on I/O, real-time control, and integration rather than on raw inference throughput, which is a reasonable reading of where reconfigurable logic actually wins.

See also

• AI accelerator
• ASIC
• GPU
• Tensor Processing Unit
• AI accelerator comparison
• Edge AI

References

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