MTIA

MTIA (Meta Training and Inference Accelerator) is a family of custom silicon chips that Meta designs for use in its own data centers rather than for sale. Meta announced the first generation on May 18, 2023, describing it as an ASIC built for the deep learning recommendation models behind its ranking and recommendation workloads; Meta framed AI at the company as ubiquitous, spanning content understanding, Feeds, generative AI, and ads ranking ^[1]. The program has since expanded from a single inference part into a multi-generation roadmap covering recommendation training and generative AI inference, and in March 2026 Meta said it had deployed hundreds of thousands of MTIA chips in production ^[5].

The chips are developed in close partnership with Broadcom ^[5] and fabricated by TSMC: the first generation used a 7nm process and the second used 5nm ^[1][3]. MTIA is not a replacement for merchant AI accelerator hardware. Meta continues to buy GPUs at very large scale while positioning its own silicon as one part of what it calls a diverse silicon portfolio ^[5], the same in-house-plus-merchant pattern followed by other hyperscaler operators with programs such as Google's TPU and Amazon's AWS Trainium.

Meta renamed the family in 2026. The chips formerly known as MTIA 1 and MTIA 2i are now called MTIA 100 and MTIA 200, and the current roadmap consists of MTIA 300, 400, 450, and 500 ^[5]. Meta says it has published research papers detailing the first two generations at the International Symposium on Computer Architecture, at ISCA 2023 and ISCA 2025 ^[5]; the first-generation paper appeared in the ISCA 2023 proceedings ^[2].

Why Meta built its own accelerator

Meta ran inference for its ranking and recommendation workloads on CPU-based servers for years. The ISCA 2023 paper describing the first MTIA chip states the problem directly: the growing compute and memory requirements of deep learning recommendation models (DLRMs) pushed the company toward specialized hardware such as GPUs or dedicated accelerators ^[2]. Meta's own framing in the 2023 announcement was that GPUs "were not always optimal for running Meta's specific recommendation workloads at the levels of efficiency required at our scale" ^[1].

Recommendation models are an unusual target. They combine dense matrix work with very large embedding tables and sparse gather operations, so their bottleneck is often memory capacity and bandwidth rather than raw floating-point throughput. That mix rewards a chip designed around the workload, which is what MTIA was: a co-designed hardware, software, and model stack aimed at the operators Meta actually runs in production ^[1][2].

The economics reinforce the engineering argument. Meta's capital expenditures, including principal payments on finance leases, reached $72.22 billion for full-year 2025, and the company initially guided 2026 capex to a range of $115 billion to $135 billion, citing investment to support Meta Superintelligence Labs and the core business ^[12]. In April 2026 that guidance was raised to $125 billion to $145 billion ^[13]. In March 2025, Reuters reported that Meta had begun testing an in-house chip for training AI systems, manufactured in partnership with TSMC; coverage of that report noted that much of Meta's planned $65 billion of 2025 capital expenditure would go toward NVIDIA GPUs, so displacing even a fraction of that spending is material ^[9].

The program has not been a straight line. Meta pulled the plug on a large-scale rollout of a custom chip planned for 2022 and instead placed orders for billions of dollars' worth of NVIDIA GPUs, which required major redesigns of several of its data center builds ^[8].

First generation: MTIA v1 (MTIA 100)

Meta says it designed the first-generation MTIA ASIC in 2020 for internal workloads and announced it publicly in 2023 ^[1]. The chip is organized as a grid of 64 processing elements (PEs) in an 8x8 arrangement, connected to each other and to memory blocks by a mesh network. The grid can run a single job or be partitioned into subgrids running independent jobs ^[1].

Each PE contains two processor cores, one of them with a vector extension, plus fixed-function units for matrix multiplication, accumulation, data movement, and nonlinear function evaluation. The cores are based on the RISC-V open instruction set architecture and are heavily customized for compute and control tasks ^[1]. Each PE also carries 128 KB of local SRAM, backed by 128 MB of on-chip SRAM shared across the grid and off-chip LPDDR5 ^[1].

An MTIA v1 accelerator has a 25 W thermal design power and is mounted on a dual M.2 board that connects to the host CPU over PCIe Gen4 x8 links and consumes as little as 35 W. Each server holds 12 accelerators ^[1].

The software stack was built around PyTorch from the start. Models were compiled through PyTorch FX IR with low-level optimization in LLVM IR, using an MTIA-extended LLVM toolchain. Meta also shipped a library of hand-tuned kernels for performance-critical operators such as fully connected layers and embedding bags, and created a domain-specific language called KNYFE for writing new kernels ^[1].

Meta's published results were measured rather than triumphant. On low-complexity and medium-complexity recommendation models, MTIA v1 was more efficient than an NNPI accelerator and a GPU, but Meta had not yet optimized the chip for high-complexity models ^[1]. The ISCA paper puts a number on it: across various DLRMs the team averaged 0.9x performance per watt relative to the GPU baseline, with individual operators such as GEMMs reaching about 2x performance per watt ^[2]. In other words, the first chip reached roughly parity on whole models while showing where a second generation could win.

Second generation: next-gen MTIA (MTIA 200)

Meta announced the next-generation MTIA on April 10, 2024 ^[3]. It kept the 8x8 PE grid but moved to TSMC 5nm, raised the clock from 800 MHz to 1.35 GHz, and rebalanced the memory hierarchy: local PE storage tripled, on-chip SRAM doubled with 3.5x the bandwidth, and LPDDR5 capacity doubled. The network on chip was also redesigned to double bandwidth and coordinate between PEs at low latency ^[3]. Meta reported that the redesigned PEs deliver 3.5x higher dense compute and 7x higher sparse compute than MTIA v1 ^[3].

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Sources: Meta's 2023 and 2024 announcements ^[1][3]. Meta's comparison table labels both the integer and floating-point GEMM rows "TFLOPS/s"; the 2023 post gives the first-generation figures as 102.4 TOPS at INT8 and 51.2 TFLOPS at FP16 ^[1]. The two posts also disagree on first-generation memory: the 2023 text says the design can scale to 128 GB of LPDDR5, while the 2024 comparison table lists 64 GB ^[1][3].

For deployment, Meta built a rack-based system holding up to 72 accelerators, arranged as three chassis of 12 boards with two accelerators each, and upgraded the fabric both between accelerators and between host and accelerators to PCIe Gen5 ^[3]. Meta reported a 3x performance improvement over the first-generation chip across four key models it evaluated, and at the platform level, with twice the number of devices and a two-socket CPU, 6x model serving throughput and a 1.5x improvement in performance per watt over the first-generation MTIA system ^[3]. Unlike the first chip, this one handled both the low complexity (LC) and high complexity (HC) ranking and recommendation models used in Meta's products, which can differ by roughly 10x to 100x in model size and compute per input sample, and Meta stated that MTIA had been deployed in the data center and was serving models in production, going from first silicon to production models running in 16 regions in less than nine months ^[3]. The engineering team presented the co-design process behind the second generation at Meta's AI Infra @ Scale event in August 2024 ^[7], and a talk on the design appeared at Hot Chips 2024 ^[4].

Software stack

The consistent thread across generations is that MTIA is programmed through the same open frameworks Meta's researchers already use, not a bespoke SDK. The second-generation stack integrates with PyTorch 2.0 and reuses framework-level machinery such as TorchDynamo and torch.export unchanged, because graph capture and transformation are hardware agnostic ^[3].

Kernel generation goes through Triton. Meta built a Triton-MTIA compiler backend to generate high-performance code for MTIA hardware, and thanks to TorchInductor developers can use Triton-MTIA in both ahead-of-time and just-in-time workflows ^[3]. By 2026 Meta described the stack as taking a PyTorch-native approach that supports both eager and graph modes, with the familiar torch.compile and torch.export used to capture and optimize model graphs; in graph mode it integrates directly with PyTorch 2.0's compilation pipeline. The compiler chain runs from Torch FX IR and TorchInductor down through Triton, MLIR, and LLVM backends tuned for MTIA, and an MTIA plugin for vLLM swaps in MTIA-specific kernels for important operators such as FlashAttention and fused LayerNorm ^[5].

The 2026 roadmap: MTIA 300 through 500

On March 11, 2026, Meta published "Four MTIA Chips in Two Years: Scaling AI Experiences for Billions," describing four generations shipping on a compressed schedule ^[5]. The company said it had built the capability to ship a new chip roughly every six months, against an industry norm of one to two years, and that the accelerators are architected as systems of chiplets: discrete, reusable blocks for compute, I/O, and networking ^[5][6].

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Across the span from MTIA 300 to MTIA 500, Meta says HBM bandwidth increases 4.5x and compute FLOPS increases 25x, the latter measured from MTIA 300's MX8 rate to MTIA 500's MX4 rate ^[5]. The generative AI parts lean hard on low precision: MTIA 450 raises MX4 throughput 75% to speed up mixture-of-experts feed-forward computation, goes beyond FP8 and MX8 to deliver six times the MX4 FLOPS of its FP16/BF16 rate, and adds hardware acceleration that eases Softmax and FlashAttention bottlenecks in attention and feed-forward layers ^[5].

At the system level, a rack of 72 MTIA 400 devices connected by a switched backplane forms a single scale-up domain, and MTIA 400, 450, and 500 share the same chassis, rack, and network infrastructure so that each new chip can drop into deployed infrastructure ^[5]. The rack and system designs align with Open Compute Project standards ^[5]. Meta also said it had onboarded numerous internal production models and tested MTIA with large language models such as Llama ^[5].

Meta's newsroom summary of the same announcement said MTIA 300 is used for ranking and recommendations training and is already in production, while MTIA 400, 450, and 500 are capable of handling all workloads but will primarily support generative AI inference into 2027. It also stated that Meta deploys hundreds of thousands of MTIA chips for inference across both organic content and ads, and framed the strategy plainly: there is no single chip that can meet all the demands, so Meta deploys a variety of chips optimized for each workload ^[6].

In July 2026, Reuters reported, citing an internal memo, that Meta was on track to start making the latest versions of its AI chip in September, with Broadcom working on the chip design and TSMC manufacturing it ^[10].

Related silicon efforts

Meta's silicon strategy extends past the accelerator itself. In October 2025, The Next Platform reported that Meta was buying Rivos, a startup founded in September 2021 that built power-optimized chips combining server-class RISC-V CPUs with a data-parallel accelerator (a GPGPU aimed at large language models and data analytics), tightly integrated through a uniform memory space spanning DDR DRAM and HBM; the deal was confirmed by Rivos investor Walden Catalyst ^[11]. The Next Platform characterized the purchase as giving Meta the foundation of its future processor designs, comparable to what Annapurna Labs became for Amazon Web Services ^[11].

MTIA also sits alongside Meta's much larger fleet of merchant GPUs. Meta's Research SuperCluster reached 2,000 NVIDIA DGX A100 systems with 16,000 A100 GPUs in its second-phase buildout, and the largest of the original Llama models was trained on 2,048 A100 GPUs over 21 days ^[8]. Meta's 2026 statements continue to describe MTIA as an important part of its infrastructure strategy rather than the whole of it ^[5].

Limitations and open questions

Public evidence about MTIA is almost entirely first-party. Meta has published peer-reviewed architecture work ^[2][4] and a series of engineering posts, but the performance claims for the 2026 generations are relative improvements over previous MTIA chips rather than measured comparisons against contemporary merchant accelerators, and no third-party benchmark results for MTIA 300 or later were public as of mid-2026 ^[5].

The historical record also argues for caution about roadmap dates. Meta cancelled a planned 2022 rollout of an earlier custom chip and moved to NVIDIA GPUs instead ^[8], and reporting in 2025 noted that several of the company's chip design efforts had been canceled or otherwise scaled back after failing to meet internal expectations ^[9]. Two of the four chips on the current roadmap, MTIA 450 and MTIA 500, are not scheduled for mass deployment until 2027 ^[5].

Finally, the workload target has shifted faster than the silicon. MTIA began as a recommendation inference part, and Meta's own description of MTIA 300 notes that ranking and recommendation was the dominant Meta workload before generative AI took off ^[5]. Chips designed for embedding-heavy, memory-bound recommendation serving are not automatically the right shape for long-context transformer decoding, which is why the newer parts pivot toward HBM bandwidth and low-precision MX4 throughput.

See also

• Meta AI
• MTIA 300 series
• AI accelerator
• Recommendation system
• AWS Inferentia
• Meta compute

References

1. ^Meta AI, "MTIA v1: Meta's first-generation AI inference accelerator," May 18, 2023. ai.meta.com/...ining-inference-accelerator-AI-MTIA
2. ^Amin Firoozshahian, Joel Coburn, Roman Levenstein, Rakesh Nattoji, Ashwin Kamath, et al., "MTIA: First Generation Silicon Targeting Meta's Recommendation Systems," Proceedings of the 50th Annual International Symposium on Computer Architecture (ISCA '23), 2023. dl.acm.org/...3579371.3589348
3. ^Meta AI, "Our next generation Meta Training and Inference Accelerator," April 10, 2024. ai.meta.com/...ining-inference-accelerator-AI-MTIA
4. ^Mahesh Maddury, Pankaj Kansal, Olivia Wu, "Next Gen MTIA - Recommendation Inference Accelerator," 2024 IEEE Hot Chips 36 Symposium (HCS). doi.org/...HCS61935.2024.10665192
5. ^Yee Jiun Song, Andrew Tulloch, Harikrishna Reddy, CQ Tang, Vijay Thakkar, "Four MTIA Chips in Two Years: Scaling AI Experiences for Billions," Meta AI blog, March 11, 2026. ai.meta.com/...meta-mtia-scale-ai-chips-for-billions
6. ^Meta Newsroom, "Expanding Meta's Custom Silicon to Power Our AI Workloads," March 11, 2026. about.fb.com/...-silicon-to-power-our-ai-workloads
7. ^Engineering at Meta, "Inside the hardware and co-design of MTIA," August 22, 2024. engineering.fb.com/...meta-mtia-hardware-co-design
8. ^TechCrunch, "Meta bets big on AI with custom chips and a supercomputer," May 18, 2023. techcrunch.com/...custom-chips-and-a-supercomputer
9. ^TechCrunch, "Meta is reportedly testing in-house chips for AI training," March 11, 2025. techcrunch.com/...g-in-house-chips-for-ai-training
10. ^TechCrunch, "Meta's new AI chips will begin production in September," July 9, 2026. techcrunch.com/...ll-begin-production-in-september
11. ^The Next Platform, "Meta Buys Rivos To Accelerate Compute Engine Engineering," October 2, 2025. nextplatform.com/...ate-compute-engine-engineering
12. ^Meta Platforms, "Meta Reports Fourth Quarter and Full Year 2025 Results," January 28, 2026. prnewswire.com/...full-year-2025-results-302673127
13. ^Meta Platforms, "Meta Reports First Quarter 2026 Results," April 29, 2026. investor.atmeta.com/...default