Thermodynamic computing

Thermodynamic computing is a family of computing approaches in which the random thermal fluctuations of a physical system, rather than deterministic switching of transistors, do the work of a computation. Where a conventional digital chip spends energy holding every bit far above the noise floor, a thermodynamic computer is built from components that are deliberately noisy: probabilistic bits (p-bits) that flip between 0 and 1 with a tunable probability, coupled oscillators that jitter around an equilibrium, or Ising-model lattices that relax toward low-energy states. The problem to be solved is encoded in the couplings between these components, and the answer is read out from the statistics of the system's trajectory or from the state it settles into ^[1][2]. The term was popularized by a 2019 Computing Community Consortium report that proposed a research agenda "centered on thermodynamics" for post-Moore computing ^[1], and it is now used by two venture-backed startups, Extropic and Normal Computing, for chips aimed at generative AI sampling workloads ^[3][4].

The field overlaps heavily with probabilistic computing, the p-bit research program associated with Supriyo Datta at Purdue University and Kerem Camsari at the University of California, Santa Barbara, and with the older literature on Ising machines, which includes D-Wave's quantum annealers, optical coherent Ising machines, and digital annealers from Hitachi, Fujitsu, and Toshiba ^[5][6][7]. IEEE Spectrum's computing editor put the relationship bluntly in 2025: thermodynamic computing may be "probabilistic computing by a new name," and the CTO of one probabilistic-computing startup told the magazine it is "this same computing paradigm" with "a new implementation" ^[8]. As of September 2026 the largest systems announced are a one-million-p-bit machine built from networked FPGAs at UC Santa Barbara ^[9], Normal Computing's CN101 digital chip running small generative models across six chips ^[10], and Extropic's Z1 chip with 269,568 p-bits, which the company says is taped out but for which it has published only simulation-based efficiency estimates and which it plans to make available for early access in 2027 ^[11][12]. Every efficiency multiplier quoted in this article is the claimant's own estimate; none has been independently measured on production silicon.

Definition and scope

The 2019 report, written by Tom Conte, Erik DeBenedictis, Natesh Ganesh, Todd Hylton, John Paul Strachan, R. Stanley Williams and 33 co-authors after a Computing Community Consortium workshop, defined the motivation rather than a device. It argued that transistors have become so small that "we are struggling to eliminate the effects of thermodynamic fluctuations, which are unavoidable at the nanometer scale," that computing consumed about five percent of the power generated in the United States, and that next-generation fabs cost more than $10 billion. Its proposal was to stop fighting fluctuations and instead "harness nature's innate computational capacity" through "complex, non-equilibrium, self-organizing systems," a program the authors named "Thermodynamic Computing" or TC ^[1].

In practice the label now covers several distinct hardware ideas that share one principle, using stochastic physical dynamics as the computational primitive ^[10]:

• Probabilistic bits, or p-bits: two-state devices whose output fluctuates between 0 and 1 with a probability set by an input. Networks of p-bits implement Gibbs sampling of an Ising or Boltzmann energy function directly in hardware ^[5][13].
• Ising machines: any physical system, quantum or classical, whose dynamics seek the ground state of an Ising Hamiltonian, used for combinatorial optimization ^[7].
• Continuous-variable Langevin computers: circuits of coupled oscillators or RC cells driven by noise, whose equilibrium fluctuations encode the solution of a linear-algebra or Gaussian-sampling problem ^[2][14].
• Digital stochastic computers: standard CMOS logic that runs stochastic dynamics (accumulators, random walks) asynchronously, keeping the mathematical structure of the analog approach while dropping the analog circuits ^[10].

The common target is a class of workloads that already use randomness. Normal Computing's 2023 "Thermodynamic AI" paper grouped generative diffusion models, Bayesian neural networks, Monte Carlo sampling, and simulated annealing under one mathematical framework and argued that stochastic fluctuations, which such algorithms must currently synthesize with pseudo-random number generators on digital hardware, "can be viewed as a computational resource" ^[2]. Extropic's launch post makes the same argument from the other direction: running a generative model "fundamentally comes down to sampling from some complicated probability distribution," and modern systems "do a lot of matrix multiplication to produce a vector of probabilities, and then sample from that," whereas its hardware "skips the matrix multiplication and directly samples" ^[3].

Quanta Magazine's July 2026 survey of the field, written by Philip Ball, separated the approaches into two branches: equilibrium thermodynamic computing, in which a system relaxes into an energy minimum that encodes the answer, "like a folding protein," and out-of-equilibrium computing, in which the system is continuously driven and "the trajectory itself encodes the calculation." Patrick Coles of Normal Computing told the magazine that nonequilibrium designs are popular because they "can potentially be faster, because you're not waiting for natural equilibration" ^[15].

Physics and theoretical background

Landauer's principle

The link between information and heat that underlies the field goes back to Rolf Landauer's 1961 paper "Irreversibility and Heat Generation in the Computing Process" in the IBM Journal of Research and Development, which argued that erasing a bit of information necessarily dissipates a minimum amount of heat ^[16]. Antoine Bérut, Artak Arakelyan, Artyom Petrosyan, Sergio Ciliberto, Raoul Dillenschneider and Eric Lutz reported an experimental verification of Landauer's bound in Nature in March 2012 ^[17]. Practical transistors switch at energies many orders of magnitude above the Landauer limit precisely so that thermal noise cannot flip them; Camsari and Datta's 2017 paper notes that conventional logic and memory are built from "magnets with energy barriers in excess of 40-60 kT" ^[5]. Thermodynamic computing proposals invert that design rule: a p-bit is, in Datta's description, a magnet made so small that it is unstable, "this seeming bug" turned "into a feature" ^[18].

Boltzmann machines and energy-based models

The algorithmic side of the field descends from the Boltzmann machine, introduced by David Ackley, Geoffrey Hinton and Terrence Sejnowski in the 1985 Cognitive Science paper "A Learning Algorithm for Boltzmann Machines" ^[19]. A Boltzmann machine is a network of binary stochastic units whose joint distribution is a Boltzmann distribution over an energy function, and it is trained by comparing correlations in the data-clamped and free-running phases. This is the same mathematical object as the Ising model of statistical physics, and it is the model that p-bit hardware and Extropic's chips sample from: Extropic describes Z1 as sampling "from an energy-based model known in the literature as an Ising model" using a chromatic Gibbs sampling algorithm executed in-situ ^[11], and Camsari's group has trained deep Boltzmann networks directly on sparse Ising machines ^[20]. Energy-based models sit alongside the Hopfield network and probabilistic graphical models more generally; Extropic's launch post says its TSUs "enable sampling from Probabilistic Graphical Models (PGMs) made of EBMs" ^[3].

Stochastic thermodynamics and Langevin dynamics

The continuous-variable branch rests on Langevin dynamics, the stochastic differential equations that describe a system subject to conservative, dissipative and fluctuating forces. Normal Computing's Nature Communications paper states that "thermodynamic computing is based on the stochastic dynamics of a physical system acted on by a combination of conservative, dissipative, and fluctuating forces" and works through the case where the dynamical variables are continuous, because diffusion models, Bayesian inference and linear algebra all involve continuous distributions ^[14]. The company's "Thermodynamic Linear Algebra" preprint (Maxwell Aifer, Kaelan Donatella, Max Hunter Gordon, Samuel Duffield, Thomas Ahle, Daniel Simpson, Gavin Crooks and Coles, August 2023) connects solving linear systems, inverting matrices and related primitives to "sampling from the thermodynamic equilibrium distribution of a system of coupled harmonic oscillators" ^[21]. Stephen Whitelam of Lawrence Berkeley National Laboratory summarized the operating principle for Quanta: if a network of coupled resonators is "shaken" by noise comparable to the coupling energies, its equilibrium fluctuations correspond to the inverse of the coupling matrix, "so you can build your device and come back sometime later and measure its fluctuations, and you've done matrix inversion" ^[15].

A 2026 preprint by Alberto Rolandi, Paolo Abiuso, Patryk Lipka-Bartosik, Aifer, Coles and Martí Perarnau-Llobet is one of the few attempts to bound the resource cost of the paradigm. It notes that "a theoretical characterization of the resource cost of thermodynamic computations is still lacking," derives limits on an energy-delay-deficiency product using geometric bounds on entropy production, and observes that the protocols that saturate those limits "require full knowledge of the final equilibrium distribution, i.e., the solution itself" ^[22].

Probabilistic bits

Camsari, Rafatul Faria, Brian Sutton and Datta introduced the p-bit as a circuit element in "Stochastic p-bits for Invertible Logic" (Physical Review X, 2017; arXiv October 2016). The paper showed that stochastic units "can be interconnected to create robust correlations that implement Boolean functions with impressive accuracy" and, unlike digital gates, are invertible: with the output clamped, "the network fluctuates among possible inputs consistent with that output" ^[5]. Writing in IEEE Spectrum in 2021, Camsari and Datta dated the start of their p-bit work to 2012, framed the p-bit as a play on the qubit, and gave the cleanest statement of the difference from quantum computing: a probabilistic computer "adds probabilities; the latter adds complex probability amplitudes," which is why probabilistic machines can run at room temperature but cannot reproduce the path cancellation that powers Shor's or Grover's algorithms ^[18]. Kaiser and Datta's 2021 review in Applied Physics Letters and the 2023 "full-stack view" by Shuvro Chowdhury and eleven co-authors survey devices, architectures and algorithms for the resulting p-computers ^[13][23].

Hardware approaches

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Probabilistic computers built from p-bits

The first hardware p-bits used stochastic magnetic tunnel junctions (MTJs), the same device used in magnetoresistive memory but engineered to be thermally unstable. William Borders, Ahmed Pervaiz, Shunsuke Fukami, Camsari, Hideo Ohno and Datta reported "Integer factorization using stochastic magnetic tunnel junctions" in Nature in September 2019, a Tohoku University and Purdue collaboration ^[6]; IEEE Spectrum later described it as a probabilistic computer with eight p-bits ^[25]. Datta told the magazine in 2022 that he used to ask colleagues in magnetic memory, "Could you give us your bad, bad devices?" ^[40].

Because coupling large numbers of MTJs is hard, the group's larger machines have been built on FPGAs. Navid Anjum Aadit, Andrea Grimaldi, Mario Carpentieri, Luke Theogarajan, John Martinis, Giovanni Finocchio and Camsari reported a sparse Ising machine in Nature Electronics in June 2022 in which flips per second, "the key figure of merit," scale linearly with the number of p-bits; the FPGA prototype was described as up to six orders of magnitude faster than standard Gibbs sampling on a CPU and 5-18 times faster than TPU and GPU approaches, and it factored semiprimes up to 32 bits ^[24]. In June 2026 Aadit, Xiuqi Zhang, Chowdhury and ten co-authors including Tathagata Srimani and Camsari posted "Programmable Probabilistic Computer with 1,000,000 p-bits," which networks FPGAs into a single Ising machine that performs Gibbs sampling "at over a trillion flips per second" while devices "exchange nothing but 1-bit boundary states." The paper's central result is a design rule: the ratio of boundary-exchange frequency to local p-bit update frequency determines whether a partitioned machine behaves like a monolithic one, and below a topology-dependent threshold residual energy still decays as a power law with a reduced exponent ^[9]. IEEE Spectrum reported that the machine runs on 18 FPGAs and quoted Aadit, then a postdoctoral scholar at Stanford, saying "our machine communicates without global lockstep synchronization" ^[25]. Spectrum, citing Camsari, wrote that unlike QUBO devices or Ising machines, probabilistic computers "are not hardwired for a single problem, but are instead programmable general-purpose machines" ^[25].

The device side has advanced in parallel. Christian Duffee, Jordan Athas, Pedram Khalili Amiri and colleagues reported an ASIC in 130 nm foundry CMOS that uses voltage-controlled MTJs as its entropy source, implementing integer factorization, in a paper published in Nature Electronics in 2025 ^[28]. In December 2025 researchers at UC Santa Barbara and Tohoku University, working with TSMC, presented a "DAC-free" p-bit at IEDM that replaces the digital-to-analog converter in conventional p-bit circuits with delay-based digital logic, which Fukami said removes "the typically used big, clunky analog circuits" ^[41]. In April 2026 Xuejian Zhang, Zhihong Chen, Joerg Appenzeller and co-authors reported what they called "the first experimental demonstration of a fully CMOS-integrated sMTJ-based P-Bit" using three transistors and one stochastic MTJ ^[26], and a group including Fukami, Ohno and Borders reported a p-bit unit cell with superparamagnetic tunnel junctions integrated in 130 nm CMOS ^[27]. On the algorithm side, Nihal Sanjay Singh, Mazdak Mohseni-Rajaee, Shaila Niazi and Camsari proposed in March 2026 replacing the independent noise of standard diffusion models with Ising-coupled Markov chain Monte Carlo dynamics that "map naturally" onto probabilistic computers ^[42].

Other groups pursue different p-bit substrates. IEEE Spectrum's 2022 IEDM coverage described spin-orbit-torque MTJ p-bits from Lang Zeng's group at Beihang University, which cut the coupling response from milliseconds to microseconds, and a flash-memory probabilistic computer from Georgia Tech, Intel and KAIST that used the intrinsic noise of FinFETs ^[40]. A team at MIT demonstrated a photonic p-bit based on an optical parametric oscillator whose phase is set by vacuum fluctuations, generating 10,000 p-bits per second; Camsari called the work "very exciting" but said he would like to see "follow-up work beyond single p-bits to correlated photonic p-circuits" ^[43].

Ising machines

Ising machines predate the thermodynamic-computing label and are usually discussed as optimization hardware rather than sampling hardware, but they share the same energy function. Naeimeh Mohseni, Peter McMahon and Tim Byrnes' 2022 review in Nature Reviews Physics groups them into classical thermal annealers (spintronic, optical, memristive and digital), dynamical-system solvers (optical and electronic) and superconducting quantum annealers, and observes that "any problem in the complexity class NP can be formulated as an Ising problem with only polynomial overhead." Its assessment was that "Ising hardware based on classical digital technologies is the best performing for common benchmark problems," with quantum approaches showing an advantage only "for particular crafted problem instances" ^[7].

• D-Wave, founded in 1999, describes itself as "the world's first commercial supplier of quantum computers" and sells superconducting annealing systems alongside a gate-model program ^[30]. It announced general availability of its Advantage2 system, which it describes as a "production-ready 4,400+ qubit annealing quantum computer," on May 20, 2025 ^[31]. Whether such machines outperform classical Ising hardware is contested; see quantum computing.
• Coherent Ising machines encode spins in the phases of optical parametric oscillator pulses. Two Science papers published on November 4, 2016 reported a fully programmable 100-spin machine with all-to-all connections (McMahon, Alireza Marandi and colleagues at Stanford) and a 2,000-node machine (Takahiro Inagaki and colleagues at NTT) ^[32][33].
• Hitachi's CMOS annealing chip, a 20k-spin Ising chip presented at ISSCC in 2015 by Masanao Yamaoka and colleagues, was an early fully digital Ising solver ^[34]. Fujitsu's Digital Annealer, described by Satoshi Matsubara and colleagues at ASP-DAC 2020, is a digital-circuit annealer offered as a service ^[35]; Camsari and Datta noted in 2021 that "companies like Fujitsu are already marketing similar probabilistic computers" built from pseudo-random circuits rather than nanodevices ^[18].
• Toshiba's simulated bifurcation algorithm, published by Hayato Goto, Kosuke Tatsumura and Alexander Dixon in Science Advances in April 2019, derives a classical Hamiltonian solver from the company's own quantum-computer proposal ^[36]. Toshiba said an FPGA implementation found a good solution to a 2,000-variable fully connected problem in 0.5 milliseconds, "approximately 10 times faster than the laser-based quantum computer" it identified as the previous record holder, and that eight GPUs solved a 100,000-variable problem in a few seconds ^[37].

Camsari's group has argued that dense connectivity of the kind used by coherent Ising machines does not scale: a 2025 Physical Review Applied paper by M Mahmudul Hasan Sajeeb and colleagues shows that "dense connectivity leads to severe frequency slowdowns and interconnect congestion" and proposes sparsifying graphs with copy nodes so that "all spins in a network can be updated in constant time" ^[44]. That constraint is why both the UCSB machines and Extropic's Z1 use sparse, locally connected graphs.

Continuous-variable thermodynamic computers: Normal Computing

Normal Computing was founded in 2022 in New York by Faris Sbahi, Antonio Martinez and Matthias Tan, former members of Google X and Google Brain ^[15]. Its chief scientist, Patrick Coles, previously led a near-term quantum computing group at Los Alamos National Laboratory; in an August 2026 essay he wrote that the NISQ bet "started from a hardware primitive and went searching for algorithms to fit it," and that he left because "if new physics was going to matter for AI, it had to arrive in this decade" ^[45]. The company's thermodynamic work began with the February 2023 "Thermodynamic AI and the fluctuation frontier" preprint by Coles, Collin Szczepanski, Denis Melanson, Kaelan Donatella, Antonio Martinez and Faris Sbahi, which identified "stochastic bits (s-bits) and stochastic modes (s-modes)" as the building blocks of discrete and continuous thermodynamic hardware and contrasted the approach with quantum computing, "where noise is a roadblock rather than a resource" ^[2]. The August 2023 "Thermodynamic Linear Algebra" preprint followed ^[21], as did preprints on error mitigation (January 2024) ^[46], thermodynamic natural gradient descent (May 2024), Bayesian inference on analog Langevin circuits (October 2024) ^[47], and second-order optimization (February 2025).

Its first hardware, the stochastic processing unit (SPU), was described in a December 2023 preprint and published in Nature Communications on April 22, 2025 by Melanson, Mohammad Abu Khater, Aifer, Donatella, Hunter Gordon, Ahle, Crooks, Martinez, Sbahi and Coles. The device is "composed of RLC circuits, as unit cells, on a printed circuit board, with 8 unit cells that are all-to-all coupled via switched capacitances," and the authors demonstrated Gaussian sampling and matrix inversion on it ^[14]. The limitations were acknowledged from the start. IEEE Spectrum reported in May 2025 that "the Normal Computing team acknowledges that this prototype is not scalable" and was removing the inductors for a silicon design ^[8], and Quanta noted that the circuit "didn't actually run on ambient noise, which was too low-level to affect the dynamics"; the researchers injected noise from a random-number generator, "which cost energy," so the prototype does not itself demonstrate the promised energy advantage ^[15].

CN101, the company's first chip, was taped out in July 2025 ^[45] and announced on August 12, 2025 as "the world's first thermodynamic computing chip" implementing the company's "Carnot architecture," with a company claim of "up to 1000x energy consumption efficiency on targeted AI and scientific workloads" ^[4]. An April 2025 roadmap post said the chip would have four compute tiles of 64 state variables each with a reconfigurable network-on-chip, supporting 256-dimensional problems with 32-bit state variables ^[48]. The August 2026 preprint "CN101 - A Digital Thermodynamic Computer for Generative AI," by Lars Holdijk, Melanson and 15 co-authors, reframes the design as substrate-independent: the equilibration-style formulation had previously been "formulated exclusively through Langevin dynamics, restricting its implementations to analogue substrates," and CN101 instead implements it "through discrete accumulator dynamics on standard CMOS using stochastic computing principles." The paper reports variational autoencoders and flow-matching models on the chip and names three hardware-level properties: precision set by how long the dynamics run, sample averages that decompose across independent trajectories, and "sequential parallelism," in which dependent stages of a computation run concurrently ^[10]. Coles' August 2026 post gives the Hot Chips 2026 numbers: a conditional VAE generating MNIST digits on one chip, and a convolutional flow-matching model generating CIFAR-10 images across six chips with pixel error near 0.06, with the hundred-layer generation reaching the same image "in 62x fewer cycles than running the layers one after another." He calls these "small-scale results" that "validate the primitives" ^[45]. The company's discretization scheme, lattice random walk (LRW), is described in a separate preprint by Duffield, Aifer, Melanson, Zach Belateche and Coles ^[49].

Normal's stated roadmap in August 2025 was CN201 in 2026 for "high-resolution diffusion models and expanded AI workloads" and CN301 in late 2027 or early 2028 for video diffusion ^[4]; by August 2026 Coles described the company's "current focus" as LLM inference and its target architecture as "stochastic analog computation in memory" ^[45]. The company raised a $50 million round led by Samsung Catalyst in March 2026 and lists "$85M+" total funding on its website, alongside an AI-driven chip-design business, Normal EDA ^[50][51]. Quanta noted that CN101 "has yet to be assessed by other experts" ^[15].

Thermodynamic sampling units: Extropic

Extropic was founded in 2022 by Guillaume Verdon, its CEO, with co-founder and CTO Trevor McCourt; both previously worked on quantum computing at Google ^[52][53]. The company is headquartered in Waltham, Massachusetts, with offices in San Francisco ^[54]. Its March 2025 disclosure to Wired was an oscilloscope trace of a single p-bit flipping between states under a controllable probability, and the stated goal was a chip "three to four orders of magnitude more efficient than today's hardware"; Wired noted that earlier thermodynamic computing efforts relied on superconducting circuits whereas Extropic uses charge fluctuations "in regular silicon" ^[52].

On October 29, 2025 the company announced X0, its first chip, and XTR-0, a desktop platform combining a CPU, an FPGA and two X0 chips, each of which Wired described as containing "a handful of p-bits" ^[53][3]. Extropic called the design "the world's first scalable probabilistic computer" ^[3]. Its thermodynamic sampling units (TSUs) are networks of pbits, each "just a random number generator," combined so that each pbit's probability is set by a bias plus a weighted sum of its neighbors' values; the chips sample from energy-based models by Gibbs sampling, and store and process information "in a completely distributed manner where communication only happens between circuits that are physically close to one another" ^[3]. The accompanying paper, "An efficient probabilistic hardware architecture for diffusion-like models" by Andraž Jelinčič, Owen Lockwood, Akhil Garlapati, Peter Schillinger, Isaac Chuang, Verdon and McCourt, proposes "an all-transistor probabilistic computer that implements powerful denoising models at the hardware level" and reports a system-level analysis indicating "performance parity with GPUs on a simple image benchmark using approximately 10,000 times less energy"; it was published in npj Unconventional Computing on July 2, 2026 ^[55][56]. The company's own post states that the 10,000x figure comes from "our simulations of TSUs running DTMs on the small benchmarks in our paper" ^[3]. The open-source simulation library, THRML, was released at the same time ^[3]; early users named by Wired included the weather-forecasting startup Atmo, whose CEO said he was "able to run a few p-bits and see that they behave the way they are supposed to" ^[53].

Z1, announced in the company's summer 2026 post "From One to One Billion," is described as a die with eight cores, 269,568 pbits, ">50 MHz sampling rate" and "<1 W" power, measuring less than twelve millimeters per side, with each pbit connected to sixteen neighbors in a sparse graph and executing chromatic Gibbs sampling in-situ. The post says Z1 "is finally taped out" and lays out a Z1 thermo compute stick (two chips, more than 500,000 pbits, M.2 form factor), a PCIe accelerator card (16 chips, more than 4 million pbits) and a billion-pbit cluster, all for early access in 2027 ^[11]. Wired had reported in October 2025 that the forthcoming chip would have 250,000 p-bits and arrive "next year" ^[53]. The same post introduced Torx, an open-source JAX framework for stochastic differentiable programming ("Torx is to THRML what PyTorch is to CUDA"), and Thermalizers, a compiler that maps Torx programs onto thermodynamic hardware and which the company says "can deliver up to 10,000x greater energy efficiency" for the right workloads ^[11][57][58]. On July 30, 2026 the company announced a non-binding letter of intent with the U.S. Department of Commerce for up to $75 million through the CHIPS Research and Development Office, whose capstone is a Z1.5 chip fabricated at a U.S. foundry; the release says two X0 variants had already been taped out and tested at two different fabs ^[54].

The September 4, 2026 Z1T release, covered in detail at Extropic Z1T, is the company's first model family designed for the chip: sparse transformer-like models with 4-bit weights and four incoming edges per output node, trained with an open recipe and with one checkpoint released as open weights on Hugging Face ^[12]. The headline "up to 140x" energy figure is an estimate that depends on the assumed utilization of the comparison GPU: about 139x against an NVIDIA H100 at 10 percent model FLOPs utilization, 28x at 50 percent and 14x at 100 percent, with Z1-only layers at 4,680x, 935x and 468x respectively. The post states the projections are "based on theoretical chip energy consumption of Z1 based on our best estimates, which are anchored to reality from our experiments with similar pbits in X0," that they exclude the dense logit readout layer, and that the FPGA co-processor "consumes the vast majority (>95%) of the energy." A batch-1 latency estimate of 58.8 microseconds per token is compared with measured H100 figures of 702 microseconds (eager PyTorch) and 102 microseconds (torch.compile) for a small model with 11.55 million body parameters, and the authors note that "if we were to batch on the GPU, H100s would be substantially more efficient" ^[12]. The Z1T post's model-details box gives the Z1 graph as 8 cores x 33,696 pbits with "2,135,904 hardwired edges," while the die captions in both the Z1 and Z1T posts say "215,904 coupling parameters"; the company has not reconciled the two figures ^[11][12].

How it differs from quantum, neuromorphic, and analog computing

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Camsari and Datta's distinction is the one most cited: a probabilistic computer sums probabilities, so adding a path "can only increase the final probability," whereas quantum amplitudes can cancel, which is "the power of quantum computing" and also the reason qubits need cryogenic isolation. Probabilistic computers "can be built with simpler technology operating at room temperature" but are "effective only for algorithms that do not require path cancellation" ^[18]. Normal's founding paper makes the same point from the thermodynamic side: quantum computing treats noise as "a roadblock rather than a resource" ^[2]. Coles has since argued that quantum "has spent a decade as hardware in search of a workload," while thermodynamic hardware starts from a workload that already exists ^[45][50].

The comparison with neuromorphic computing is closer than the one with quantum. Both reject the separation of memory and compute; Extropic says its TSUs "store and process information in a completely distributed manner" ^[3], and Normal describes "compute with memory, asynchronous" as a design principle ^[51]. The distinction is what the local dynamics are: a neuromorphic core emulates neuron and synapse dynamics, while a thermodynamic core samples an energy function. Zhang and colleagues frame probabilistic computing as one of the "novel computing schemes" sparked by "the rise of neuromorphic computing" ^[26]. Analog in-memory computing with memristor crossbars shares the promise of energy savings and the problem of noise, but treats device noise as an error to be corrected; a 2026 Nature Materials review notes that analog compute-in-memory "typically struggles with achieving high accuracy at the same time, owing to the noise-sensitive nature of analogue computing" ^[59]. Normal's continuous-variable SPU is itself an analog computer, but one in which the noise is the point ^[14].

Claimed applications

The workloads named across the field cluster around sampling:

• Generative AI. Both startups target diffusion and related models. Extropic's DTM paper and Z1T release ^[55][12], Normal's CN101 results with VAEs and flow matching ^[10], Whitelam's generative thermodynamic computing framework ^[39] and Camsari's correlated-diffusion proposal ^[42] all put image generation first. Coles argues diffusion is "a probabilistic workload on hardware engineered to be deterministic" and therefore "where the mismatch is widest" ^[45].
• Bayesian inference and uncertainty quantification. Normal's 2024 preprint proposes analog devices that "sample from Bayesian posteriors by realizing Langevin dynamics physically," motivated by the intractability of sampling posteriors over many parameters ^[47]; see Bayesian inference and variational inference.
• Combinatorial optimization. The historical Ising-machine workload: Max-Cut, satisfiability, spin glasses, scheduling and routing ^[7][9][25].
• Monte Carlo simulation and scientific computing. Verdon told Wired that "the most computationally-hungry workloads are Monte Carlo simulations" and that the company is interested in "simulations of stochastic systems in high-performance computing at large" ^[52]; see Markov chain Monte Carlo. Weather forecasting (Atmo) and molecular applications, including an Extropic preprint on codon optimization, are cited as examples ^[53][11][62].
• Linear algebra and training. Normal's linear-algebra, matrix-exponential and second-order-optimization papers extend the paradigm to matrix inversion and K-FAC-style optimizers, which are not inherently probabilistic ^[21][14].
• Discriminative inference on Ising hardware. A June 2026 preprint by Andrew Moore reports training convolutional networks for "thermodynamic inference on Ising machine hardware," reaching 94.9 percent on CIFAR-10 and 76.0 percent on CIFAR-100 under binary Gibbs sampling, and derives an accuracy-versus-inference-cost relation ^[60].

Criticisms and open questions

Scale of the evidence. Every efficiency claim in the field rests on simulation, projection or small prototypes. Extropic's 10,000x figure is from simulations on small benchmarks ^[3][55]; its Z1T figures are theoretical estimates anchored to X0 measurements, with the FPGA rather than the thermodynamic chip consuming more than 95 percent of the energy in the modeled system ^[12]. Normal's "up to 1000x" is a company target ^[4], and its published chip results are MNIST and CIFAR-10 generation ^[45]. Whitelam, whose simulations Quanta summarized as dissipating "by a rough comparison, about 100 billion times less" heat than a digital neural network (IEEE Spectrum put the same work at "one ten-billionth the energy"), told Quanta that "you could build a thermodynamic computer from real springs" and told IEEE Spectrum that "we don't yet know how to design a thermodynamic computer that would be as good at image generation as, say, DALL-E," and that near-term designs "will be something in between that ideal and current digital power levels" ^[15][61]. Quanta's summary of CN101 was that "the device has yet to be assessed by other experts" ^[15].

Precision and error. Analog thermodynamic hardware inherits the precision problems of analog computing. Normal's 2024 error-mitigation paper states that "a key source of errors in this paradigm is the imprecision of the analog hardware components" and proposes a method to reduce the error from linear to quadratic dependence on that imprecision ^[46]. The company's move from the analog SPU to the digital CN101 was in part a response to this, trading analog noise for pseudo-random digital dynamics ^[10]. On the p-bit side, device-to-device variation in MTJs is a recurring problem; Zeng's group told IEEE Spectrum "each device had its own character, just like human beings," and both the Beihang 1-bit-quantized coupling scheme and the UCSB-Tohoku DAC-free design are explicitly workarounds for variability ^[40][41].

The digital co-processor. Present systems are hybrids. XTR-0 pairs two X0 chips with an FPGA and a CPU ^[53]; Z1T's decode pipeline runs embeddings, residuals and the vocabulary readout on an FPGA and only the sparse sampled projections on Z1 ^[12]; the UCSB million-p-bit machine is itself built from FPGAs with no physical fluctuating devices ^[25]; and the SPU's noise came from a digital random-number generator ^[15]. Whether the thermodynamic part can absorb enough of a real workload to dominate the energy budget is the open engineering question, and Extropic's own post says removing the FPGA bottleneck is "future algorithmic and hardware explorations" ^[12].

Model compatibility. Coles has criticized p-bit approaches for "requiring users to train new models suited to the hardware," arguing that Normal builds "for the models people already run" ^[45]. Extropic's Z1T is precisely such a hardware-specific model family, trained with custom sparse architectures and a scaling law "with the added sweepable variable of connectivity" ^[12]. Which strategy wins depends on whether the efficiency gains justify retraining.

Scaling and connectivity. Fixed, sparse hardware graphs constrain which models can be embedded, which ties model sparsity to the silicon ^[12][44]; dense graphs slow down ^[44]; and multi-chip probabilistic machines need boundary synchronization rules that were only quantified in 2026 ^[9]. Rolandi and colleagues' resource bounds show that the protocols that saturate the energy-time-accuracy limits require knowing the answer in advance ^[22].

Naming and novelty. The relationship between "thermodynamic" and "probabilistic" computing is itself contested. IEEE Spectrum's Dina Genkina wrote that the two are "essentially the same paradigm" with a cultural difference: probabilistic-computing groups "almost exclusively trace their academic roots" to Datta's group at Purdue, while Normal's founders "come from backgrounds in quantum computing" ^[8]. Ludwig Computing's CEO said of Normal's prototype, "It's amazing what they have done," but that "there is a lot to be worked to really take it from what it is today to a commercial product" ^[8].

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References

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